TOOLS AND TECHNOLOGIES

Products and services for system design

Digital communications design tools Synopsys unveiled new system-level design implementation technologies that enable designers at the system level to build complex communication systems using synthesizable building blocks and estimate the silicon complexity early in the design cycle. The new technologies will be shipping in the next release of COSSAP. With the new COSSAP synthesizable digital communications library, designers will have access to over 160 optimized models directly synthesizable with Behavioral Compiler. The models include such complex functions as QAM and QPSK modulators and demodulators, as well as synchronizers. The COSSAP hardware implementation package, which includes Asset system-level synthesis, advanced integration into Behavioral Compiler, and the synthesizable fixed-point communications library, will be available early in 1998 for $70,000 list. Existing COSSAP customers will be upgraded at no charge. Synopsys Inc., Mountain View, Calif. Contact (960) 962-5000 or www. Synopsys .com.

3-D extraction The newest version of the Fire & Ice full-chip 3-D extraction product line expands support for deep-submicron ASICs and ASSPs. Enhancements provide overnight turnaround of extraction for all nets, with no loss of modeling accuracy. In addition, Fire & Ice is now integrated with standard place-and-route and timing analysis tool suites. It now enables designers to limit extraction to the minimum set of interconnect parasitics required for accurate timing analysis so that designers can make tradeoffs between the speed and depth of the design, and also now allows net-by-net extraction. A new interface, based on the LEF/DEF, DSPF, and RSPF formats, improves the timing accuracy between synthesis and place-and-route iterations. Fire & Ice is available in production volume now. Prices for Fire & Ice start at $150,000. Simplex Solutions Inc., Sunnyvale, Calif. Contact (408) 617-6100 or www.simplex.com.

Laser-programmable gate arrays The CX2002 LPGAs are intended as a cost-reduction solution for the 0.6-µm CX2001 LPGA family. The devices, which have the same architecture and cell structure and use the same netlist as the CX2001, are manufactured with a 0.5-µm, three-layer-metal CMOS process and are priced from 7 millicents per gate in high-volume production. They offer up to 160,000 usable gates plus up to 128 kbits of embedded configurable high-speed memory and as many as 536 I/Os. They also feature analog PLL capability, full-scan ATPG, low power consumption, and the flexibility of mixed 3- and 5-V programming. A range of packaging types are available, including PQFP with up to 304 pins, PGA with up to 391 pins, and BGA with up to 352 pins. Chip Express Corp., Santa Clara, Calif. Contact (408) 235-7348 or www.chipexpress.com.

DSP development tool DSP Blockset version 2.0 is a major upgrade to the DSP Blockset, Simulink block libraries for designing, simulating, and prototyping digital signal processing systems. The new version includes a number of new libraries and blocks that enhance the ability to model both discrete-time and hybrid systems, including support for adaptive and multirate filtering, a matrix math library, signal processing blocks for time and frequency domain modeling, spectral analysis blocks, and new building blocks such as switches and counters. It also provides many performance and functionality enhancements, including more efficient buffering, rate conversion blocks, improved handling and faster processing of complex value signals, and simplified block user interfaces and library organization. DSP Blockset v2.0 is available now for Windows 95 and NT PCs; Macintoshes; and Sun, HP, IBM, Silicon Graphics, and DEC Alpha workstations. For PC customers in North America, the price starts at $395. The MathWorks Inc., Natick, Mass. Contact (508) 647-7000 or info@mathworks.com.

Configuration EPROM The EPC1441 configuration EPROM was designed for low-cost configuration for the new Flex 6000 family of programmable logic devices. The chip offers 441 kbits, so that one part can be used to configure devices of up to 30,000 gates, including Flex 8000 family devices and appropriate members of the Flex 10K family. It is available now in a 32-pin TQFP, 8-pin PDIP, or 20-pin PLCC, priced at $3.50 each in 100-unit lots. Altera Corp., San Jose, Calif. Contact (408) 544-7000 or www.altera.com.

Rad-hard gate arrays The UTO.6µCRH commercial radiation-hardened gate array family is designed for high-reliability space applications that require SEU immunity and 100,000 rads of total dose hardness. The family offers array sizes of 3,400 to 400,000 usable gates and is radiation-hardened to 1.0 ⁵ rads (SiO ₂ ) total dose (functional) and SEU immune cells to less than 1.0 ^­10 errors/bit/day. It features clock rates of up to 150 MHz and operating voltages of 5V and 3.3V. It also features JTAG (IEEE 1149.1) boundary-scan registers built into the I/O and low-noise, high-pin-count package technology for fast, high-density circuits. A cell library with over 170 options includes SSI, MSI, and 54xx equivalent functions, as well as configurable RAM, MIL-STD-1553 functions, microcontrollers, and other macro- and mega-cells. UTMC Microelectronic Systems, Colorado Springs, Colo. Contact (800) MIL-UTMC or www.utmc.com.

VHDL simulation The upgraded Voyager 2.5 series of VHDL simulators provides interoperability and flexibility through support for the Foreign Procedural Interface (FPI). FPI eases the integration of add-on solutions into the customers' design flow, and the company is working with providers of testbench generation tools, graphical user interfaces, and power estimation tools. The series is used in conjunction with the NSIM hardware accelerator and consists of the Voyager VS, a VHDL simulator; the Voyager CS mixed-level simulator; and Voyager CSX, a mixed-level software simulator with seamless integration to NSIM. Voyager VS sells for $9,500, Voyager CS for $22,000, and Voyager CSX for $27,000. Ikos Systems Inc., Cupertino, Calif. Contact (408) 366-8535 or www.ikos.com.

Library generation Symbol Genie and Geom Genie use templates to save time and reduce errors in the generation of new parts. Symbol Genie allows on-the-fly creation of new schematic symbols that can be inserted into the design environment. Geom Genie assists librarians by allowing the easy creation of new parts and group editing of existing parts. Geom Genie also allows retargetting of geometry libraries to different manufacturing sites using the group editing feature. The list price of Symbol Genie is $45,000, including the Symbol Genie Server and Axel symbol and template compilers. Geom Genie lists for $35,000. Mentor Graphics Corp., Wilsonville, Ore. Contact (800) 547-3000 or www.mentorg.com.

integrated system design  November 1997