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A Picture Is Worth a Thousand Megabytes Designers need tools that improve their productivity and raise the level of abstraction for verification as well as design. by Robert M. Gardner

New HDL design analysis tools must be developed to cope with increasingly complex deep submicron designs--and they must do so without injecting a significant latency between the time the designer poses the question and the time the design analysis tool provides the data.

To cope with increasingly complex designs, the design process must start at increasingly higher levels of abstraction. As a result, the chasm between the initial high-level description and the gate-level implementation is widening. What's the problem? The cost of finding and fixing a bug increases by an order of magnitude each time the design proceeds to the next, lower level of abstraction. Since there are typically three or four levels of abstraction between the initial design entry and design sign-off, the cost of detecting and correcting an error can increase by a factor of 100 to 1,000 as the design proceeds. An essential part of the designer's and the EDA vendor's job is to detect and correct errors as early in the design as possible.

As designers increasingly move to HDL-based designs, EDA vendors will need to develop graphics-based tools to allow designers to visualize problems at all levels of abstraction, from initial design entry through implementation.

In order for these new HDL design analysis tools to deal accurately, reliably, and quickly with the new design paradigm, there are some crucial technical issues which will need to be addressed. At the million-transistor level, designers will need to be able to efficiently trace a problem through multiple levels of abstraction. Graphical "trace browsing" is an important method to allow designers to visualize problems by generating virtual schematics from behavioral- through gate-level HDL code. The tool must also be highly interactive, which implies an efficient design verification database. The tool must respond with the right data within seconds of the request. Many minutes of delay is no longer acceptable to the designer, and the accompanying schedule delays are not acceptable to engineering management.

I suggest when evaluating graphical design analysis tools, one should be careful not to be "wowed" by pretty pictures. Take a close look at the overall performance of the graphical tool, using a large design as a benchmark. You will want the tool you learn to use today to remain useful as your design complexity increases.

Graphics-based design analysis tools and their underlying design verification databases are the technological keys to drastically improving design and verification time, and to the corresponding reduction in time to market, for multi-million transistor designs in the near future. Designers need to be able to visualize design problems and to explore the verification database quickly and efficiently while debugging HDL code. It is imperative that EDA tool developers provide tools that get information to the designers quickly and accurately. This is no easy task given the increasing density and complexity of these new designs. EDA vendors such as Design Acceleration (San Jose, CA) must answer the designer's call for tools that accelerate the design cycle, and we have to do so now if we're to serve our user community faithfully. *

Robert M. Gardner is president and CEO of Design Acceleration Inc. (San Jose CA).

To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@isdmag.com.

integrated system design  March 1997