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The Next Frontier: High-Level Functional Verification Specialized functional verification tools have become a necessity. by Daniel Chapiro

Simulation, synthesis, and timing tools are viewed as the core set of tools for submicron designs. However, to cope with increasingly complex systems, we need to include tools for functional verification in this set of core tools.

Functional verification can be approached with static or dynamic methods. Static verification includes equivalence checking and theorem-based formal verification approaches. Dynamic verification includes all the simulation-based approaches. Static approaches are complementary to dynamic approaches, but they do not replace them because it is too risky to go to tape-out without any simulation.

Most companies use HDLs for design and functional verification. However, HDLs such as Verilog and VHDL were not designed with verification as a top priority. They were made to describe hardware, mainly for design purposes. Users have filled many gaps by augmenting them with C/C++, Perl, etc. Going from schematics to HDLs and synthesis has reduced the time to market. Now we need to make similar progress with hardware verification languages (HVLs) created expressly for verification.

To catch more design errors we need to decouple testbenches from design, capture the design invariants so that we can verify model properties, and then stress the design extensively. For complex systems, verification typically takes more resources and time than the design. Also, the cost of undetected design errors has skyrocketed. Hence, there are valid economic reasons for tools dedicated to verification.

Other approaches, such as automatic, constraint-driven testbench generators, seem appealing at first. However, if you look a bit deeper, they are not as useful as they might seem--sweeping through valid addresses might help fault coverage, but it does little to catch design errors. The main difficulty is to test the design with the real-life conditions it will find in a system--introducing external events, interrupts, resets, etc. We need to create boundary conditions to verify that no unexpected value changes happen and that no illegal transitions occur. The key issues in finding difficult bugs are concurrent control, sequencing of interleaved operations, and checking of conditions, rather than just automatically generating heaps of vectors. The design community needs high-level HVLs and related verification tools that are designed from the ground up for verification.

Testbenches written in HVLs should be compact and highly readable as well as independent of the design implementation. HVLs should be built on top of existing standards such as C, C++, and Verilog. They should not reinvent the wheel. They should also allow reuse of existing code, such as Verilog bus-functional models.

For the verification manager, the bottom line is "...have we created all the stressful conditions that our design will find in the field, and does it do what it should?" The economic implications of adopting new HVLs such as Vera--and the technologies that address the above question faster and with higher certainty--are large. Thinking "what worked so far will be fine for the next generation of designs" will prove to be a costly mistake. HVLs are the next frontier, and the companies that take advantage of them will have an edge over their competitors.

Daniel Chapiro is CEO of Systems Science Inc. (Palo Alto, CA).

To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@isdmag.com.

integrated system design  April 1997