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Programmable Logic Synthesis: Your Competitive Weapon Shrink-Wrapped synthesis tools can give you an advantage over your competitors. by Al Graf

The use of programmable logic burgeoned in the last decade because it revolutionized the system design process. It is truly a "process" innovation, rather than a "product" innovation. Today talented designers are in short supply and manufacturers must maximize their designers' productivity to win. More new products introduced per designer per year means your firm will grow faster than your competitors. Any competitive advantage resulting from product innovation is short lived, as products are easily and widely reverse engineered. Accelerating the process of bringing new products to market has become critical if you want to reap financial returns before increasingly nimble competitors can respond.

The next innovation, "shrink wrapped" synthesis tools, has arrived to accelerate programmable logic design, and these tools will increase the quality of the finished design. The availability of these tools presents another opportunity to gain a competitive advantage.

HDLs have allowed designers to adapt a true hierarchical, top-down design methodology that simplifies the conceptualization of complex designs. Since coding a behavioral VHDL design is completely analogous to writing a computer program in a high-level computer language, functions and procedures can be written that, once debugged, can be reused many times, as in any computer programming methodology. The availability of quality synthesis for different architectures means that the designer can reuse the same code for any target device without making modifications to accommodate the specific architecture being targeted. And use of a standard language such as VHDL means that completed designs can be easily transferred to a new tool or implemented in a different manufacturer's silicon without rewriting the design. Multiple behavioral VHDL design approaches can be clearly organized within a single block of code by writing each option as procedures or code blocks which are "commented out" until they are to be evaluated. This approach also clearly documents the options tried in the source code. All of these benefits of HDL design give designers the freedom to experiment with a wider range of design options. HDL source-level simulators also offer the ability to find logic flaws earlier and fix them more quickly, resulting in higher quality, more robust designs.

No longer must users sacrifice performance or logic efficiency when using synthesis for PLDs. Any modern tool will support architecture-specific module generation. This is the ability to recognize behavioral descriptions of specific logic functions such as adders, comparators, counters, etc. and then create the synthesized representation that maps most efficiently to the target device. For example, the UltraGen module generator in Cypress Semiconductor Corp.'s (San Jose, CA) Warp synthesis tool implements synthesized modules for a variety of architectures, depending on the user's selection. The synthesis approach taken also differs for a given architecture, depending on the choice of optimization goal (minimum area or maximum speed) chosen for each subsection of the design.

The efficiency of design with programmable logic has been further enhanced by the availability of high-performance architecture-specific synthesis. The global competitive game requires users of programmable logic to "get on the synthesis bandwagon" or risk being left behind.

Al Graf is the Manager of Programmable Logic Planning and Applications at Cypress Semiconductor Corp. (San Jose, CA).

To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@isdmag.com.

integrated system design  June 1997