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Breaking the Interconnect Barrier High-density interconnect creates new analysis requirements. by Marty Walker

Moore's law assures us that process technology will continue to meet the inexorable demand for cost-effective ICs of incredible complexity. Market forces--particularly those resulting from the blurring of the computer, consumer, and communications markets--are once again causing IC manufacturers to re-tool, this time for as much as $1.5 billion per fab area, so that they may reliably meet this demand.

Don't feel assured. Moore's law assumes that advances in design methodologies, and especially in EDA tools, will keep pace with process advances. But in the back room, engineers designing chips for the new deep submicron processes are beginning to encounter the "interconnect barrier"--the point where today's design tools run afoul of plain, old physics. Where designers before could predict with confidence how a complex circuit would perform when manufactured, they now find uncertainty. This uncertainty already severely compromises the power and value of the new processes.

At the heart of the problem is on-chip interconnect. With designs built on older 1.0-µm processes, only 10 percent of design performance was directly determined by the interconnect. Now, however, 60 percent of chip performance is determined solely by the interconnect, and the old interconnect models don't work.

Why? It's a question of scale. Beyond the interconnect barrier, interconnect demands a 3-D analysis based on the physics of the interconnect. Today's production EDA tools do not have such grounding in fundamental physics, and use simple approximations that are inadequate at deep submicron scales to predict interconnect performance. As a result, performance information is unreliable, and designers are forced to make pessimistic estimates to ensure that their chips function. Previously, such pessimistic estimates had little impact on chip design, but now, when interconnect dominates performance, such pessimism can increase design time, slow chip performance, and increase die size.

For example, one advanced ASIC design group incurred a six-month delay because they could not get closure on the timing performance of their design. Others report design tradeoffs that have 30 percent extra chip areas that are caused by inaccurate estimates of interconnect performance. A 30 percent die size increase can double manufacturing costs, thereby reducing the ROI on a $1.5 billion fab by half. The impact of each of these on the bottom line has been enormous. Therefore, the interconnect barrier is a problem for senior executives, as well as designers.

Is there hope? Yes. Two critical elements are required to break the interconnect barrier. First, a new technology is needed that correctly captures the actual, 3-D physics of the interconnect, and efficiently abstracts interconnect performance information from the design. IC manufacturers, working hand in hand with providers of this technology, are able to accurately model the interconnect performance of deep submicron chip manufacturing processes. Second, commercial EDA tools based on this technology are needed to help designers predict chip performance within 10 percent of reality, versus the ±30 percent with alternative tools. With such technology, it becomes possible to break the interconnect barrier.

Marty Walker is the president and co-founder of Frequency Technology Inc. (San Jose, CA).

To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@isdmag.com.

integrated system design  July 1997