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FPGAs Penetrate the Production-Volume Gate Array Market Submicron lithographies are benefitting the performance, density, and cost of field-programmable devices. by John Birkner

The latest generations of FPGAs use technologies that suit them to applications previously seen as appropriate only for gate arrays. Numerous new devices with higher logic capacities, faster performance, and lower costs have enabled FPGAs to replace gate arrays in products with higher production volumes and higher speeds than previously possible. In fact, several leading market researchers have forecast that revenues for FPGAs will surpass that of gate arrays by the year 2001.

Nearly all leading high-density FPGA companies manufacture their products at commercial foundries, as opposed to most gate array companies, which use their own fabs. In the past, in-house fabs have allowed gate array makers to have an advantage of one to two process generations over the fabless FPGA companies, making gate arrays both faster and cheaper. However, because of the growing wafer production volumes now manufactured at the commercial fab consortiums used by the FPGA companies, those fabs have been able to invest in the latest deep-submicron processes. That kind of investment becomes increasingly difficult for gate array vendors to match as construction costs for state-of-the-art fabs continue to escalate. The latest processes have allowed FPGAs to narrow the gap with gate arrays in performance, density, and cost.

Cost and available logic density are tightly coupled with a device's die size. It's estimated that 25 to 50 percent of gate array designs are pad-limited, meaning that the amount of silicon used by a design easily fits within the perimeter of the die as defined by the device's I/O pin bonding pads. In the past, FPGA die size has been determined by the silicon required for the logic and programmable interconnect rather than by bonding pad perimeters. With the new lithographies, however, FPGAs have also become pad-limited. The latest devices with transistor-based interconnects are pushing the limits of in-line bond pad geometries, while the latest devices using metal-layer interconnects are pushing the limits of staggered bond pads in the same way as gate arrays.

Comparable die sizes for comparable pin counts mean that popular pin-count packages can deliver large amounts of programmable logic for a cost similar to that of a gate array. Furthermore, as lithographies continue to shrink, an increasing amount of programmable logic will fit within the bond pads. As a result, a steadily increasing number of applications can benefit from the flexibility of a programmable device at a price similar to that of a custom-mask gate array.

In-system performance has been another limiting factor that has prevented FPGAs from encroaching upon traditional gate array applications. In the past, the principal determinant for gate array speed was transistor performance, with gate arrays having faster transistors because of their smaller process geometries. But with transistor lithographies (and performance) now approaching parity at deep-submicron levels, interconnect delays have become the dominant factor in device performance. Although field-programmable interconnects will never have as low an impedance as a gate array's all-metal interconnect, technologies based on low-impedance metal-layer-programmable interconnect closely approach the performance level of gate arrays.

Deep-submicron lithographies are shifting the balance of power in the ASIC world. High-density FPGAs now nearly match gate arrays in performance and cost, yet still deliver flexibility and fast time to market. *

John Birkner is vice president and cofounder of QuickLogic Corp. (Sunnyvale, Calif.).

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integrated system design  December 1997