ASIC Design

The use of static RAMs in ASIC design is a mature, well-understood process. However, the success of the layout is limited when the capability of the process or the size and number of RAMs are insufficient to meet performance requirements. As deep-submicron (DSM) design continues to progress toward RTL sign-off, the ASIC supplier must automate the RAM design methodology to make implementation issues transparent to the designer.

In the era of DSM, it is rare for chips not to incorporate SRAM. Indeed, up to 80 percent of the transistor content of 0.35- and 0.5-µm designs can be RAM, although RAM generally represents only 30 percent of the overall die. An ASIC library is no longer complete without a full menu of flexible SRAM compilers. The use of soft, firm, or hard cores--now common--is a natural extension of the standard ASIC library, which typically comprises macrocell gates and memories. Designing the control logic, datapath, and state machine for DSM ASICs, designers must understand the key role embedded memories play in the ASIC design process and the potential problems they pose.

Figure 1	Asynchronous SRAM read-write pulse generation
For asynchronous SRAMs, the read/write signal must meet the minimum pulse width requirement in a given clock cycle without violating the address setup and hold times.

The right technologies

End-user functionality, performance, size and configuration, cost, and time to market are the key factors that determine the type of embedded memories the ASIC designer uses. For example, RAM functionality will define the RAM port configuration--one, two, or more ports--which in turn affects perfomance. (Multiport RAMs are slower than single-port versions because of the extra read/write lines accessing the memory cell.)

Performance, size, and configuration requirements, on the other hand, affect the selection of design technologies: sea of gates, embedded array, or standard cells. Embedded arrays and standard cells allow the use of cell-based RAM, which produces smaller and faster functions than do the metalized sea-of-gates architectures. Therefore the choice of technology can significantly affect the die size, overall cost, and performance.

After choosing the appropriate technology, the designer must decide upon a design flow and choose from a variety of vendors' RAM offerings. A top-down synthesis-based RTL design flow for synchronous designs requires SRAM that allows the user to define the RTL code based on clock frequencies and ensures that the RAM read and write cycle times will meet the clock cycle at the RT level. Synchronous RAMs also safeguard the designer from having to manually generate write cycle pulses required with asynchronous RAMs, one of the technical challenges posed by asynchronous RAMs, along with the requirement to manually instantiate the RAMs into the RTL code.

Designers usually use asynchronous RAM with legacy code that already includes the asynchronous structures or personal design style. Figure 1 shows a typical circuit generating a write pulse consistent with the data setup time, write cycle hold time, and minimum write cycle pulse width of an asynchronous RAM. The pulse must meet the write cycle setup and data hold times of the asynchronous RAM to avoid timing violations and meet the RAM's target frequency.

Figure 2	Achieving high fault coverage
Fault coverage is poor in embedded SRAMs owing to undetectable faults on the memory's upstream logic paths and to a lack of observability on its address input pins. A multiplexer can be added and an AND gate inserted (b) to allow the address signals to propagate.

When creating high-frequency designs, the designer must closely review the vendor's asynchronous RAM parameters or, better yet, use synchronous RAMs, which have built-in write pulse timing and are considered "synthesis-friendly."

Putting RAM to the test

Meeting RAM timing is not the only issue to consider when generating RTL code. RAM testability schemes can affect RAM timing, the thoroughness of RAM test vectors, and back-end failure analysis. The experienced designer addresses testability issues up front, rather than expecting the ASIC vendor to provide ready-made solutions.

The goal of every ASIC vendor is to ensure high-quality ASICs and to achieve 100 percent fault coverage. Partial scan insertion, built-in self-test (BIST), I _ddq , and boundary scan are the most frequently used testability methodologies.

When performing full or partial scan insertion during synthesis or postprocessing, it is important to remember that ATPG algorithms see RAMs as black boxes. Since the goal of scan-based ATPG is to detect possible fault defects, the scan chain must stimulate the embedded fault and propagate it through combinational logic for detection. The presence of RAM prevents the scan chain from stimulating a possible fault and blocks all faults that are upstream from the RAM.

To achieve high fault coverage, it is therefore necessary to bypass the RAM by adding multiplexers to the address pins so that all faults are controllable and observable (see Figure 2). If the RAM has a power-down or pass-through mode, which allows the data to propagate to the outputs, the mode can be used to provide controllability and observability for the faults propagating to the data pins.

BIST for DSM

By far, the most popular RAM test scheme is BIST, which relieves the designer of the concern for RAM testability and puts the responsibility of providing for adequate automatic test solutions in the hands of the ASIC vendor. BIST insertion tools have improved significantly with the evolution of design tools and are prevalent at leading ASIC vendors.

Although BIST is the methodology of choice in DSM designs, muxed-access testing, which requires the designer to insert multiplexers at each RAM input terminal, is still popular. A major disadvantage of muxed-access testing is that it requires manual effort to instantiate the multiplexers. The delay on the datapath due to the muxes and the number of pins required to implement the test are other drawbacks. The RAM terminals may be accessed by existing functional pins, but it may be difficult to locate 64 inputs pins, 64 output pins, and associated address pins to connect one 128-word X 64-bit RAM if the chip itself has less than a 176-pin package.

On the other hand, one important advantage of muxed-access testing is the ability to fully access the RAM for silicon verification. Large RAMs occupy 100 percent utilized silicon and therefore have a higher potential for silicon defects compared with straight logic, even in today's class 1 multibillion-dollar fabs. Muxed-access testing allows the use of more extensive external test vectors to detect possible faults, whereas a BIST routine runs a specific algorithm that can't be modified to test specific faults.

Figure 3	RAM BIST macrocell
The overhead for RAM BIST drops proportionally with the number of memories used, since only one BIST controller is needed.

Still, most DSM designers prefer BIST because of its ease of use and reduced turnaround time. Whereas muxed-access testing requires pin access to all RAM terminals, BIST generally requires only 11 pins. Also, the test pattern length of BIST algorithms is shorter than that of muxed-access testing, but the gate count overhead is higher.

BIST can be implemented as either hard or soft macrofunctions. Hard-macro implementations include the test structure as part of the RAM itself. One benefit is that timing is predefined and doesn't vary based on layout or floorplanning. In addition, the ASIC vendor can customize the transistor size to reduce the impact of the BIST structures on timing. However, hard-macro RAM BIST can increase the gate count in the case of multiple RAMs, since the BIST control function is duplicated for each occurrence of the RAM. In addition, soft-macro RAM BIST allows testability to be inserted (or not inserted) for the actual BIST logic. Also, third-party BIST tools are more readily available for soft-macro implementations.

Figure 3 shows a RAM BIST scheme that assumes multiple RAMs. As shown, the single BIST controller can be shared among multiple RAMs. In the case of numerous RAMs, the overhead associated with BIST is far less than the overhead for muxed-access testing. It is important to note that the RAM BIST implementation shown includes testability pins to allow scan insertion into the BIST controller. When judging RAM testability schemes, it is important to check whether the testability structure itself is testable.

A unified approach

A unified approach encompassing BIST, full scan, partial scan, and boundary scan will further simplify overall DSM testing. New design tools automate unified testability insertion at the synthesis stage. Previously, testability tools relied on netlist postprocessing, which increased the design turnaround time. As with any insertion approach, it is important to verify the design's timing after the testability structures are inserted. If the testability structure is inserted at the initial synthesis stage, only a single prelayout verification need be performed.

To minimize DSM layout effects and achieve the required accuracy, the floorplanning session must include a detailed logic placement. To avoid surprises during layout and physical verification, a floorplanning session linking synthesis must drive the overall design flow. The importance of layout information during floorplanning is magnified by the presence of multiple RAMs, because the RAMs block critical timing paths, making clock balancing more difficult. Furthermore, access to I/Os is obstructed, and overall layout utilization is lower. For multiple-RAM designs, timing verification using gate-level simulation or static timing analysis will show the full impact of the layout.

To minimize DSM layout effects and achieve the required accuracy, the floorplanning session must include a detailed logic placement. A vendor's floorplanner library should include busing structures around the RAMs for actual layout to facilitate detailed placement. Placement software is most valuable when the actual layout uses the same algorithm. Also, since wire load delay is the predominant delay factor in DSM technology, it is beneficial to have RAM compilers that provide flexible RAM aspect ratios. The ability to change the shape of RAMs allows you to optimize the floorplan and layout.

Ron DiGiuseppe currently serves as senior manager for ASIC application engineering at Oki Semiconductor in San Jose. Before this, he spent four years as a design engineer at Raytheon Semiconductor and two years as a product engineer at NEC Electronics. He has written several papers on industry issues associated with ASIC design and development.

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integrated system design  March 1998