Cover Story

Addressing the Effects of Signal Integrity in Deep-Submicron Design As they move into the deep-submicron realm, designers need new tools and techniques that will detect and remedy signal interference. by Lynne Green

For designers, signal integrity means clean data, or put another way, a lack of signal integrity means corrupted data. In any high-speed circuit design, signal integrity is a major concern. In the early days, signal integrity was primarily an issue in RF board design. Today, as circuit design continues to migrate to deep-submicron IC scales, maintaining signal integrity is an even greater challenge. To prevent problems later on, designers need to locate sources of signal interference early in the design cycle. That will become possible as design tools and techniques improve.

Historically, designers have used two approaches to solving signal integrity problems: the RF solution, which has focused on transmission lines, and the digital solution, which has focused on package selection. Those two options, however, have fallen short when it comes to addressing signal integrity problems in deep-submicron design. To ensure signal integrity at that level, designers need to consider circuit design, placement and routing, and circuit simulation. In circuit and system design, designers can, for instance, designate the number of simultaneous switching outputs. When it comes to correcting interference through placement and routing, though, the designers' task becomes more difficult. The necessary tools don't yet exist, so the most obvious option is to be careful and methodical during circuit simulation.

For the I/O pad design group here at the Duet Technologies' IP Infrastructure Business group, signal integrity has proven to be an ongoing issue for library design. Our silicon library design tools must be able to meet the requirements for simultaneous switching outputs (SSOs), because a user may switch 16 or more 4-mA pads sharing a single V _dd and ground pad set depending on switching speed and signal integrity requirements. Deep-submicron ICs deliver the speed, but higher processing speeds lead to higher edge rates at the chip boundary, so overcoming signal interference is always a primary concern.

The issue of signal integrity
In practice, signal integrity problems often show up as pattern-dependent, or soft, errors, which are not repeatable and therefore difficult to isolate. Another way of looking at such problems is that signal integrity failures introduce "free" transitions, leading to either "bad" data being captured into a latch or a "bad" clock edge causing data to be captured at the wrong time.

The origins of signal integrity problems lie in the circuit interconnections (wires, substrates, and wells). After all, a wire serves not only as a conductor of electrons, but also as a resistor (at low frequencies), a capacitor (at midrange frequencies), an inductor (at high frequencies), and an antenna (at very high frequencies), all of which can affect signal integrity. The challenge for designers is to isolate the source of possible interference and head it off before it causes problems within a design.

For example, when thinking of a wire functioning as an inductor or antenna at high frequencies, the question becomes how high is "high"? One way of estimating which effects are dominant is to look at the wire's impedance at various frequencies. A package interconnect might have 5 (omega) + 50 pF + 10 nH. At a frequency of 100 MHz, the corresponding impedances are [5, -j32, +j6]. All three terms are comparable in magnitude. As a general rule, the larger the series (R and L) terms and the smaller the shunt (C) term, the more significant each term becomes. For digital switching edges, the frequency used in this calculation is typically 10/tr, where tr is the signal rise time.

Figure 1	Simulated switching waveform
The quiescent line shouldn't cross the logic low-level line (the dashed line) or the logic high-level line (the dotted line). Because here the quiescent line does cross the logic low-level line, data errors or clocking errors may occur. It's acceptable, though, for V dd and GND to cross those logic levels, as long as they are connected only to the output drive FETs.

When looking at signal integrity as it relates to silicon, one has to consider a fundamental problem. A lack of signal integrity causes a signal to violate a voltage constraint. In the simulated switching waveforms in Figure 1, note that both the quiescent and switching lines ring. The ringing frequency is set by the load capacitance and the package inductance (v = 1/=LC). The switching waveform exhibits both overshoot and undershoot, and the quiescent waveform exhibits ringing. An I/O cell must be designed so that the quiescent waveform does not cross V _OL or V _OH during SSO operation, where V _OH and V _OL are the output-high and output-low voltages for the I/O interface specification (V _OH = 2.4 V and V _OL = 0.4 V for TTL).

Figure 2	Capacitance vs. wire size
As ICs move to deeper-submicron features, the 2D effects and 3D effects become more important. Here, A is the classic area-only term; B and C show the effect as the wire becomes thinner and spacing decreases.

The SSO specifications must be set so that the chip doesn't reach latch-up. The switching signal must not cross V _OL or V _OH more than once, or multiple transitions may be observed by the next latch or gate. (The integrity of the switching signal is critical if the signal is a clock input.) The quiescent signal also must not cross either V _OH or V _OL to keep it in a known digital state.

That's just one example of the challenge that signal integrity poses to designers. The secret to maintaining signal integrity is applying a combination of better design tools and better design techniques.

Interference in deep-submicron circuits
As ICs scale below 0.5 µm, signal integrity becomes more of a challenge, mostly because of the faster rise times and the underlying physics of silicon design. Timing in particular becomes more sensitive to wiring parasitics as chip designs move into the very deep submicron domain (0.25 µm and below). Also, at that size, ground bounce increases because of faster signal rise times and package parasitics.

In any silicon design, resistance is caused by the interaction of the current-carrying electrons with the atoms and crystalline grains in the metal. As we shrink features below 0.5 µm, surface effects may cause the resistance of a piece of metal to decrease more slowly than the cross-sectional area, resulting in a loss of signal integrity. Foundries are addressing that problem by changing the metallization, incorporating new metals that minimize resistance.

Another factor affecting signal integrity in chip design is capacitance. Capacitance is the result of the closeness of structures with independent voltages. A reduction in design rules has two effects: First, as wires become smaller, capacitance becomes dominated by the wire spacing dimensions. Second, as the spacing between wires decreases, capacitance increases (see Figure 2). In the domain of deep-submicron design, wiring capacitance is dominated by fringing instead of area, meaning that traditional capacitance calculators can be off by a factor of two or more (high or low, depending on the net).

As silicon foundries move to five and six layers of metal, capacitance calculations become more complex. For example, for the metal cross section shown in Figure 3, a piece of metal on layer 4 may be completely shielded from the substrate by intervening wiring. Thus it's no longer sufficient to calculate capacitances to the substrate. Instead, capacitances are dominated by internodal effects, so the calculations have to be adjusted accordingly.

For example, the center metal segment on layer 4 has its capacitance dominated by four adjacent wires on metal 3, metal 4 (both left and right), and metal 5. None of those can be overlooked in calculating the capacitance on that electrical net. Today, chip designers must use 2D or, better yet, 3D field solvers to extract those capacitances. In the future, foundries need to provide internodal capacitances, including fringing as well as area effects.

Figure 3	Very deep submicron wire layers
The cross section shows a six-layer copper interconnect in a 0.25-µm process. The height-to-width ratio of the wiring indicates the importance of 3D capacitance extraction for that process. Photo courtesy of Motorola, Inc.

Inductance remains a concern primarily at the package and board levels and is dictated by both the size of the wire and the distance to the return path (usually another wire nearby or, in the case of silicon, a substrate/ground plane). As ICs scale below 0.5 µm, inductance can become significant. Inductances of even a few nanohenries on-chip can be a problem if they're in an I/O pad, where high switching currents in the power rails can produce V _dd and ground noise that can be coupled into quiescent logic. When two wires run in parallel, there's also a mutual inductance, which can couple noise onto a quiescent line. To calculate inductance, I typically use the approximation:

L = (µ ₀ )/(2 [pi] ) ln(8H/W + W/4H)

where H is the height of the metal above the silicon and W is the metal strip width. However, the approximation is not very accurate for deep-submicron design, where H is larger than W.

Crosstalk, a signal integrity problem that grows with both increasing chip clock speeds and decreasing design rules, is the result of capacitive and inductive coupling between adjacent wires, which causes each wire to act as an antenna. Crosstalk is typically observed as a fast dV/dt in one wire, which causes a second wire to respond. At 0.5 µm, that can be adequately modeled as pure capacitive coupling (displacement current). However, as dimensions shrink to 0.18 µm, inductive coupling becomes significant as well. Unfortunately, most IC-level 3D field extractors are not being used to extract inductance, so designers won't realize there's a problem until a design fails.

That means that the best strategy for dealing with crosstalk is to spot the failure using a 3D extractor and then to perform simulation. Some 3D extractors can get inductance, but designers typically don't use that feature until they've been burnt once. Some signal integrity analysis tools are now coming on the market, but they have to be used on the completed layout, which all too often is the day before tape-out.

The rule of thumb for dealing with crosstalk is that below 10 MHz on boards and 100 MHz on chips, it isn't a major issue, but above 100 MHz on boards and 1,000 MHz on chips, it is known to be significant. For anything in between, crosstalk is a definite risk, especially at the I/O interface, because that's where you see board-level as well as chip-level effects. As sizes scale down, though, such rules of thumb lose their validity.

Substrate coupling also generates signal integrity problems that grow worse with scaling. Because the substrate and wells have a finite resistivity, any current flow will cause a voltage drop. A MOSFET's threshold (turn-on) voltage depends on the effective voltage of the substrate (or well) immediately below the gate region, which means that any substrate current can shift not only the threshold of the MOSFET, but also the threshold of the logic gate or clock circuitry. As dimensions are scaled down, often the vertical dimensions are also scaled down, increasing the resistance of the substrate and well layers.

A new strategy
There is a silver lining to the cloudy issues surrounding signal integrity and circuit design. Since larger R, L, and C values are found on printed circuit boards, there's a long list of available solutions, stretching from those used for early RF boards to those employed on today's multilayer digital boards. IC designers, particularly those designing I/O cells, have been modeling package parasitics for a decade or more, and IBIS users have worked hard to develop models for packages and I/O cells.

Traditionally, two classical approaches have been used to solve the problems of signal integrity for chip and multichip module designers. The RF solution has tended to emphasize transmission lines, using impedance matching at the package boundaries. The digital (broadband) solution has emphasized care in package selection, controlling the number of simultaneously switching outputs and/or switching speeds and the use of decoupling capacitors between V _dd and ground at the external package pins.

As designers address the problem of signal integrity in deep-submicron designs, they've found that those solutions are no longer adequate. For example, limiting dI/dt, though greatly improving ground bounce and crosstalk, limits the clock speed. That means new approaches must be adapted for deep-submicron design. For example, the problem of increasing substrate resistance can be addressed by using silicon-on-insulator (SOI) technology, a proven technique in microwave IC design. Unfortunately, IC designers rarely have the option to change the foundry process.

So what are deep-submicron designers to do? The signal integrity problem can be addressed in three ways: circuit design, placement and routing, and simulation.

Addressing signal integrity in deep-submicron design
In circuit design, designers have more choices and can control signal integrity by designating the number of simultaneous switching outputs, the maximum dI/dt and dV/dt of each cell, and so on. Designers may also choose to use differential signals for high-fanout blocks, such as clock drivers. The most common example is positive-ECL signals for clocks, or full-swing differential. Both can be used on-chip as well as off-chip.

In placement and routing, the choices are more difficult. For example, crosstalk can be improved by routing sensitive nets perpendicular to noisy nets, but how does one do placement and routing to achieve the desired signal integrity? Rule-driven routers have only recently become available for printed circuit boards, and although there are some rule-driven routers for ICs, we've yet to see an IC router that is driven by user-defined rules or that supports signal integrity analysis. At the same time, the place-and-route tools must incorporate full parasitic extraction (preferably near-3D) to allow accurate prediction of slew rates (since it's slew rates that drive signal integrity) as well as delays. The ultimate router would not only have accurate parasitic extraction, it would also incorporate a signal integrity tool that would rip up and reroute if signal integrity fell below the desired threshold.

The third and most obvious solution designers can apply is to simulate circuits with care. If there's no accurate parasitic extractor, then it's up to the designers to estimate the correction factors. For example, in one study we conducted, we found that 3D capacitances (actually, 2D with some 3D effects) were about twice the value obtained using area-to-substrate-only effects. Therefore, during simulation all capacitances should be modeled as internodal, rather than as capacitances to ground. That will allow observation of crosstalk effects on quiescent nodes, as well as give more accurate delay and slew rate predictions.

Finally, simulation must be done on the circuit in its package environment. That pushes the final validation of the signal integrity from IC designers to the IC users. It also benefits the IC designers because the simulation results will more closely correspond to the test results when the silicon comes back from the foundry. As clock speeds increase, that becomes one of the critical validation or verification steps.

As IC dimensions continue to scale down, maintaining signal integrity presents more of a challenge for circuit designers. Since signal integrity problems often appear as unrepeatable errors, it becomes more important to fix problems before silicon is fabricated. That means that designers will be required to spend more time on issues such as simultaneous switching control, simulation, and packaging before chip fabrication.

To further complicate matters, scaling will increase resistance and inductance without significantly decreasing capacitance, so that layout to minimize wire length will become even more critical. At the same time, new routing rules to minimize quiet nets in parallel with noisy nets will have to be added to physical design tools to overcome signal integrity problems in deep-submicron design. And guaranteeing that a design meets signal integrity requirements will require routers that incorporate signal integrity checkers.

As designers continue to shrink circuits down to deep-submicron levels, simulation will no longer be sufficient to validate signal integrity. A silicon prototype must be used. Signal integrity data must appear on data sheets, and the signal integrity characteristics must incorporate package information to be useful to the user community.

Although we have a long way to go before the EDA industry develops the design tools, signal integrity verification strategies, and databook information formats required to address the challenges of signal integrity in deep-submicron design, significant progress has already been made. The proliferation of parasitic extractors (both 2D and 3D) is an indication of the willingness of EDA vendors to respond to industry needs. Over the next two or three years, the industry should see interesting developments in the evolution of cell design, place-and-route tools, and verification tools.

Lynne Green is CMOS circuit analysis and development engineer for the IP Infrastructure Business Group of Duet Technologies, Inc. in Bellevue, Wash. Previously, she served as president of Green Streak Programs, a consulting company specializing in Spice modeling and circuit simulation and as a staff engineer providing modeling and simulation for CMOS products at IBM.

To voice an opinion on this or any Integrated System Design article, please email your message to miker@isdmag.com.

integrated system design  June 1998