Special Section

The New Commandment in Design: Know Thy Silicon Vendor Designers now need thorough understanding of a vendor's fabrication. EDA vendors must play their part by tightly linking to both the design and silicon manufacturing communities. by Basant Chawla

In the good old days of ASIC development, an engineer could create a design in blissful ignorance of where it would be eventually fabricated. But those days are gone forever as silicon processes delve into the subterranean depths of deep and very deep submicron design.

Leading-edge microprocessors are now at 0.25 µm, and memory designers--those forerunners of what is to come--are currently working at 0.18 µm. If that weren't enough, 0.10-µm design is already in the experimental stage. But as geometries grow smaller and transistors faster, the interconnect begins to have a greater effect on circuit performance. In particular, 3D parasitics play a bigger role.

As a matter of fact, in a 0.25-µm design, the analog effects of the interconnect, such as crosstalk, delay, and degraded signal integrity, can account for up to 90 percent of the overall impact on the signal performance. And what affects the performance of the interconnect? It is the parasitics--the distributed resistance, capacitance, and inductance--created by the physical technology of the silicon fabrication process. As a result, it is getting much more difficult to predict the performance of a design during the simulation phase.

The industry's increasing reliance on third-party intellectual property (IP) will magnify the role silicon manufacturing plays in the quality of the final design. Using IP, designers will have even less control over the details of the design, forcing them to rely more heavily on their silicon provider to produce the desired performance.

It is this increasing complexity in design, brought about by the physics of deep-submicron design and the growing popularity of third-party IP, that demands a closer working relationship between designers and silicon vendors. The new golden rule in design is, therefore, "Know Thy Silicon Vendor." ASIC designers must get to know their silicon vendors, and get to know them well. A thorough understanding of a vendor's fabrication process will enable designers to more likely achieve their performance and yield goals, in addition to enjoying first-pass success. To support this relationship and help it flourish, EDA vendors must be tightly linked to both the design and silicon manufacturing communities.

Recognizing the growing role of the silicon and IP vendors in ASIC design, this year's Design Automation Conference to be held June 15­19 at San Francisco's Moscone Center has expanded to address the EDA, electronic system, and semiconductor industries. William Spencer, chairman of Sematech, will address the interdependence of silicon and design during his keynote address on Tuesday, June 16. In addition, this year's executive panel will include two representatives from the semiconductor industry, who will offer different perspectives on the future of EDA. The technical program also has expanded to include panels and papers on a wide variety of semiconductor issues. Expanded as well is the DAC exhibition area. It will include a new section for semiconductor manufacturers, called Silicon Village.

Silicon Village will be home to approximately 25 semiconductor companies, many of whom are first-time DAC exhibitors. This unique venue creates a space where the key players in the world of ASICs, FPGAs, and CPLDs--the designers, silicon vendors, and EDA software companies--can come together to work on solving the new challenges in design.

There couldn't be an easier way to fulfill the mandate to "Know Thy Silicon Vendor" than coming to DAC this year. So come prepared to ask questions, make valuable contacts, and learn. I look forward to seeing you there!

Basant R. Chawla is the 1998 DAC general chair and the director of Enterprise Information Technology in the Chief Information Office organization at Lucent Technologies, Inc. in Warren, N.J. Before that, he was the head of the Computer-Aided Engineering and Design Department at AT&T Bell Laboratories. During his 30 years at AT&T and Lucent, he has made numerous contributions to the software and the technical infrastructure of computer-aided IC design. He was a co-recipient of the 1977 Guillemin-Cauer Prize Paper Award for his work on the MOTIS timing simulator and has been a Fellow of the IEEE since 1990.

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integrated system design  June 1998