Special Section

Now in its 35th year, the Design Automation Conference continues to evolve to meet the changing needs of designers. The electronics industry's shift toward system design and away from isolated hardware and software engineering is reflected in the show's technical program, which has added panels and papers on semiconductor issues, for example.

The 35th annual DAC will take place in San Francisco's Moscone Center from June 15 to 19 and will feature a technical program consisting of technical papers, embedded tutorials, and panel discussions organized in five parallel sessions. A design tools track features new techniques for enhancing the performance and capabilities of EDA tools. Perhaps most useful for designers and engineering managers will be the design methods track, which will focus on the results and insights gained by applying EDA tools to actual system designs. Included in the technical program are eight panel discussions covering topics ranging from intellectual property to electrical noise and signal integrity.

The design methods track comprises 22 sessions covering some of the hottest topics among today's designers, including system-level design, the measurement and improvement of design productivity, functional verification, hardware/software codesign, and deep-submicron design. In addition, the DAC's University Design Contest will debut this year as Session 3 in the design methods track. Tuesday afternoon, representatives from the University of California at Berkeley, the University of California at Los Angeles, the University of Hannover, and the University of Toronto will present the designs that they have developed from concept through operational implementations. The designs span diverse application areas, including wireless systems, DSPs, and microprocessors.

Six sessions on Tuesday
Tuesday, June 16, begins with an executive plenary panel in the morning titled "Customers, Vendors, and Universities: Determining the Future of EDA Together." Panel members include a representative from U.C. Berkeley, as well as executives from Alcatel Microelectronics, Cadence Design Systems, Intel, Mentor Graphics, and Synopsys . Discussion will center on how EDA can continue to support rapid innovation in the electronics industry. Panelists will explore such questions as, What are the design challenges ahead? What new EDA technologies and working relationships are required for customers and universities to meet those challenges? What do customers want from vendors? And conversely, What do vendors want from their customers? The panel will be an hour-and-a-half-long exchange of ideas on the issues that will shape the future of EDA.

Six sessions of the design methods track take place throughout Tuesday afternoon, including the University Design Contest.

Session 4, "Embedded System Design and Exploration," takes places early Tuesday afternoon and includes papers from Delft University of Technology, U.C. Berkeley, the University of Washington, and a joint paper from Alcatel Telecom and IMEC. Topics include successive formal reinforcement of embedded systems using Java and a new algorithm for mapping a specification on a heterogeneous multiprocessor architecture.

Deep-submicron noise
Attendees of Session 5 will get a double dose of information regarding noise in deep-submicron designs. "Taming Noise in Deep-Submicron Digital Designs" offers an embedded tutorial on methodologies for reducing noise in digital ICs presented by a professor at Columbia University. Following that is a panel discussion on the noise issues involved in the design of circuits and interconnect, as well as the trade-offs that must be made between noise immunity and performance. Panel members include technologists from Columbia University, Digital Equipment, Hewlett-Packard, IBM, Intel, Metaflow Technologies, and Sun Microsystems.

Designing a system on a chip produces problems in dealing with the management of diversified design teams that include system designers, IP (intellectual property) providers, and IC designers. Such designers want to use the best tools, and they also need to combine their efforts and methodologies to make the overall design succeed. Late Tuesday afternoon, Session 8 presents new ideas for very large scale collaborative design environments, hardware/software codesign, and tool encapsulation. "Environment for Collaborative Design" includes papers from Queensland University of Technology, U.C. Berkeley, and the University of Washington that will help designers grasp the complexities of using frameworks and the Internet for broad-based projects.

As designs continue to grow, design verification remains one of the most complex and time-consuming portions of the design process. Functional verification has allowed users to validate their designs early and often. Session 9, " New Methods in Functional Verification," showcases papers from IBM, Ikos Systems, KAIST, and Synopsys . The papers present methods on how to improve the speed and effectiveness of functional verification, including a discussion on how to make functional models work on real target systems.

Embedded system designers are implementing increasing amounts of functionality with software. The issues, challenges, trade-offs, and solutions involved with such integration will be discussed in Session 10, " Hardware/Software Codesign--The Next Embedded System Design Challenge." The panel--representatives from the Alta Business Unit of Cadence, Coware, Honeywell, Omniview Design, and Wind River Systems--will offer perspectives from system designers, hardware design tool suppliers, and software development tool vendors. For example, panel members will discuss such issues as whether automatic hardware/software partitioning tools can replace the work that engineers do, exactly how much value hardware/software codesign provides without an effective interface to synthesis, and if commercial real-time operating systems are affecting hardware and software trade-off decisions.

A full day on Wednesday
Wednesday will have eight design methods sessions, including several panel discussions. Session 14 starts early Wednesday morning, and its four papers deal with recent tool and methodology developments applied to the design of DSPs and microprocessors. Topics to be discussed during "Processor Design and Simulation" include full-chip timing verification of a 600-MHz microprocessor, a top-down design environment for developing pipelined datapaths, and the design methodology used to create Hitachi's 200-MHz superscalar microprocessor.

One could argue that analog design is a skill that too few of today's engineers have mastered. So it's no surprise that Session 15, "How Much Analog Does a Designer Need to Know for Successful Mixed-Signal Design?" deals with that subject. On Wednesday morning, a panel of experts from Cadence, Carnegie Mellon University, DSM Technologies, Linear Technology, Silicon Graphics, and Texas Instruments will ponder the questions raised by the growing number of mixed-signal design teams. For instance, Do digital designers know enough about what an analog circuit is supposed to do to replicate its functions in digital CMOS? Do analog designers know enough to control voltages and current in digital CMOS?

Later Wednesday morning, three papers in Session 19, "Design Optimization for DSP," will discuss how to optimize computationally intensive DSP problems early in the design cycle. Interactive optimization at the behavioral level, a methodology based on C++, and an architectural approach for image processing will be described.

Formal verification offers exciting new options for designers facing the verification hurdles posed by large IC and system designs. Although formal verification methods are beginning to be used by leading-edge companies, questions still linger about the technology's effectiveness and ease of use. Session 20 is a panel discussion among a variety of users from around the globe. "User Experience with High-Level Formal Verification" will be a lively exchange of first-hand knowledge, with emphasis on what has been achieved and how design teams cope with changes in the design flow. Panelists will describe how they've been able to change from using tools as postdesign checkers to using them as proactive aids in achieving quality designs in less time. Panel members will be from Bosch Telecomms, Brunel University, Cisco Systems, Fujitsu Labs, Intel, Nortel, Siemens, Silicon Graphics, and Wright Patterson Air Force Base.

Wednesday afternoon begins with Session 24, "Practical Optimization Methodologies for High-Performance Design." As high-performance design continues to stress the capabilities of conventional tools, users have to develop innovative design methodologies. The session includes five papers. The first describes a unified methodology for process and circuit optimization. The remaining papers present practical solutions for the problems of timing improvement in standard-cell circuits, repeater insertion, and datapath synthesis.

Session 25, which also takes place early Wednesday afternoon, explores the black art of RF design. "RF IC Design Methodology" begins with an embedded tutorial presented by an authority from the U.C.L.A. that will outline the special challenges faced by RF IC designers. Then, experts from Lucent Technologies and Viewlogic Systems will describe the issues surrounding RF design tools, including electromagnetic modeling and signal integrity simulation.

Wednesday wraps up with two more design methods sessions. In Session 29, "Low- Power Design Using Multiple Thresholds and Supplies," three papers will explain techniques for optimally assigning supply voltage and selecting threshold voltages to make the proper trade-offs among performance, active power dissipation, and standby power dissipation. In one paper, representatives from Toshiba will detail the design methodology used in creating the ultralow-power MPEG4 codec core using voltage scaling techniques.

System-on-a-chip design
System-on-a-chip design requires changes in reuse methodology and EDA technology. As a result, the traditional roles of foundries, ASIC suppliers, and EDA vendors are blurring. For end users, that translates into both greater risks and greater opportunities. In Session 30, a panel of representatives from the leading suppliers of embedded silicon IP solutions will discuss practical expectations for system-on-a-chip design and identify the key pieces in the industry infrastructure that are needed to realize the technology's full potential. Topics will include customer expectations, standards, EDA technology implications, legal barriers, the challenges of incorporating third-party IP, and practical reuse methodologies.

Thursday morning begins with a topic close to the heart of every deep-submicron designer. In Session 34, "Interconnect Analysis and Reliability in Deep Submicron," authors from the Massachusetts Institute of Technology, TI, and the University of Rochester will present papers that describe the design considerations and analysis of inductance and electromigration of deep-submicron interconnections. All three papers will impart sound advice--figures of merit to characterize the importance of on-chip inductance, how to minimize the impact of inductance on signal delay, and a practical approach to static signal electromigration analysis.

Design productivity
A panel discussion will also take place Thursday morning in Session 35. The topic is a sticky one. "Design Productivity: How to Measure It, How to Improve It" will try to shed light on a rather abstract metric. Panelists from Cadence Spectrum Design, Cisco, Collett International, LSI Logic, Motorola, and Nvidia will review the practices and strategies that they use today to improve productivity and time to market. They will attempt to answer such questions as, What kind of measurements are being used today? What are the results? Are those measurements useful? Is there a consensus about the kinds of measurements that should be taken? And, What kind of metrics are needed? Discussion will include approaches to measuring productivity from both a quantitative and qualitative perspective.

"Practical Experience of Functional Verification for Complex ICs" will be presented in Session 39, late Thursday morning. The session examines experiences and results with functional verification methods used in two high-performance microprocessor designs done by Digital Equipment and IBM and a large ASIC design implemented by Nortel.

The start-up experience
Have you ever dreamt of starting the next Cadence or Synopsys ? Session 40, which also takes place late Thursday morning, features a panel discussion that will appeal to anyone interested in how EDA ideas become viable products. "The EDA Startup Experience: The First Product" will place the spotlight on six veteran EDA entrepreneurs who will discuss their own experiences in bringing a first product to market. Learn how Chronologic, Design Acceleration, Magma Design Automation, Senté, Synplicity, and 0-In Design Automation cut their teeth in the competitive EDA marketplace. Where did their ideas come from? Who were their competitors and their partners? Did they adopt industry standards or create new ones? How did they use advertising, trade shows, and the Internet to promote their products?

Thursday afternoon begins with two sessions from the design methods track. As feature sizes shrink and clock rates grow, power dissipation quickly becomes a limiting factor in IC design. In Session 44, "Power Dissipation and Distribution in High-Performance Processors," experts in IC power management from Digital Equipment, Intel, Motorola, Simplex Solutions, and Somerset Design Center will explain the sources of power dissipation, as well as power management techniques. They'll also address the challenge of reliably distributing power on the chip.

Session 45, "Test Challenges in the System Chip Era," offers both an embedded tutorial and a panel discussion. First, an authority from Logicvision will talk about system-on-a-chip test strategies. Then a panel of experts from around the world will debate the system-level chip test solutions that exist today. Topics will include the challenges associated with testing chips with predesigned virtual components, the viability of today's solutions, and the ability to realize the time-to-market gains offered by design reuse without test reuse.

Protecting IP
With gate counts moving into the multimillions, the exchange of intellectual property is a necessity for designing systems on a chip. But how is IP protected? Session 47, "IP Protection Technologies," is one of the two last design methods sessions and features two papers from U.C.L.A. and one paper from Northwestern University. Information to be presented includes techniques for watermarking IP to prove ownership and encrypting IP to discourage reverse engineering.

New design methods are difficult to evaluate without real data. Session 48, "Case Studies of New Design Methods," attempts to fix that problem by examining real case studies and benchmarking approaches for four novel design techniques.

Session 49 is in honor of DAC's 35th birthday. It takes place late Thursday afternoon at the same time as Sessions 47 and 48. Attendees will enjoy three presentations by long-time contributors to the EDA industry: Bryan Preas of Xerox PARC, Ron Rohrer of Intersouth Partners, and Alberto Sangiovanni-Vincentelli of U.C. Berkeley. The presenters will review the industry's past accomplishments and also look ahead to the future. There will be a panel session after the talks.

There are many other sessions of interest over the three-day technical program: Session 7, "Synthesis Flow in Deep-Submicron Technologies"; Session 11, "System-Level Power Optimization"; Session 21, "Bridging the Gap Between Simulation and Formal Verification"; and Session 43, "Technology Mapping for Programmable Logic." In addition, Friday offers six full-day tutorials on such topics as "Design Validation Techniques," "Design of Complex Mixed-Signal Systems on a Chip," and "Finding Design Errors and Locating Defects: The Same Detective Story."

For additional information, visit the DAC Web site at www.dac.com, send e-mail to dacinfo@dac.com, or call (800) 321-4573 or (303) 530-4333.

Lisa Maliniak has been a freelance writer for the past two years, covering EDA for various electronic industry trade publications, companies, and organizations. Prior to that, she spent eight years as the EDA editor for Electronic Design magazine.

To voice an opinion on this or any Integrated System Design article, please email your message to miker@isdmag.com.

integrated system design  June 1998