asic design

Bringing up an ASIC Prototype With months of effort at stake, designers should keep in mind several guidelines to tame the chaos of the ASIC evaluation and characterization process. by Kenneth Ngoc Nguyen and James M. Fenton

At long last, the moment of truth is fast approaching. The ASIC prototypes are due back any time; once they arrive, the design team will be working feverishly day and night to evaluate and characterize them. So now is the time to get everything in place to ensure a thorough yet efficient assessment of the new design. Having the right equipment and a well-thought-out procedure helps to streamline that crucial and usually frenetic stage in the design cycle.

The overriding concern when bringing up an ASIC is to be sure that it be fully evaluated without consuming too much of the total schedule. By the time an ASIC becomes a prototype, the system design cycle is usually well past the midway point. Any delays that far downstream that interfere with design completion can pose a significant threat to successfully meeting target introduction dates. In other words, the more prepared the design team is for bringing up the ASIC, the better.

Unfortunately, no two designs are alike, posing a challenge to defining guidelines for evaluation and characterization. The design team must consider numerous variables that depend on what type of ASIC they've created. For example, it sometimes makes sense to use an oscilloscope, whereas other situations demand a logic analyzer. So during characterization, the design team must constantly make trade-offs between how much data to gather and the impact on the design schedule. What if it finds a problem in an ASIC? It can choose from many different paths when faced with that dreaded situation (see "Every ASIC Designer's Nightmare").

Even though diversity is about the only constant in ASIC design, design teams can still follow some broad guidelines for a more effective ASIC evaluation and characterization process. Based on Tektronix's experience with hundreds of ASIC designs, we've developed some guidelines that provide a general methodology for bringing up a prototype ASIC design. The basic steps in this process include:

• testing for fundamental manufacturing flaws
• examining the IC in its system environment
• evaluating basic operations
• running the chip at full system speed
• assessing performance

Adherence to the methodology can ensure efficient and thorough prototype evaluation.

The first step in evaluation is typically performed not by the designer, but by the layout team, which places the chip on an IC tester and runs a basic functional test. Here, the goal is to determine if the manufacturing process has caused any fundamental flaws, such as stuck at 1, stuck at 0, or bridges.

The tester uses test vectors to control the behavior of the chip. Though the vectors generated from the ASIC simulation should be fairly comprehensive, elusive manufacturing flaws might slip by an initial examination. The designer, then, should remain on the lookout for manufacturing flaws further on in the evaluation.

Besides controlling the ASIC's behavior, the tester also provides a view into the ASIC's functionality. The tester flags any unexpected functional behavior and brings it to the attention of the layout team. Problems encountered at the initial stage must be immediately and exhaustively tracked down. Manufacturing flaws are usually quite subtle but can destroy the performance of the ASIC and any other devices fabricated with the same process.

Environmental impact

If the ASIC passes muster in the preliminary functional test, it's then delivered to the ASIC designer, who must carefully examine its functionality.

At this point the ASIC is usually soldered onto the target system board, which contains a microprocessor and external memory along with other circuitry. The system board now supplies the stimuli for the functional testing. The designer needs external test and measurement equipment to observe the ASIC's outputs and verify the solder connections to confirm the absence of misconnections, shorts, or opens. That step is a pedestrian but extremely important task, because an incorrect connection could profoundly distort the performance of the ASIC. The designer must take special care to ensure that power and ground aren't shorted together, using an advanced voltage meter to check for appropriate voltage and current.

The designer can now power up the prototype system and assess the quality of the clock line. An oscilloscope is the right tool for the task, especially for today's faster applications, which may supply clock rates exceeding 50 MHz. That rate translates into cycle times of 20 ns with edge rates approaching subnanosecond speeds. To obtain a clear picture of waveform activity this fast, an oscilloscope with a bandwidth of at least 1 GHz or better is necessary.

Figure 1	Unterminated clock
The DSO waveform display shows two clock signals in the same system: one (upper trace) with a well-terminated transmission line; the other (lower trace) with a poorly terminated transmission line. The designer may modify the clock line distribution layout, change the driver used, add termination, or determine that the design contains sufficient margin to tolerate the signal distortion.

Probing concerns first surface at this point. ASICs come in all different sizes and package styles. With pin counts moving into the hundreds, it's no easy task to securely attach probes to an IC. If the designer is probing a typical high-speed design with edge rates around or below 1 ns, the loading of the probe itself can decrease the performance of the signal being measured. That is, the probe's inductance and capacitance can noticeably skew a high-speed signal going into or out of the ASIC. Consequently, it's important to select a probe--usually a low-capacitance probe--that exacts minimal loading on the IC while providing a secure, solid connection. During the probing of higher-frequency signals, it's very important to make the connection with as short a ground lead as possible to avoid degrading the signals.

Figure 2	Data bus breakdown
Bringing up an ASIC PrototypeUsing a high-resolution logic analyzer, the designer can quickly zero in on setup and hold violations across hundreds of signals. Here a 64-bit data bus fails to meet a critical setup time requirement. A built-in oscilloscope allows the designer to then view all the details concerning both the clock and the last signal to settle on the data bus.

To more effectively accommodate probing during ASIC evaluation, a little foresight during the design of the system circuit board goes a long way. Placing probes at critical points on the board--for instance, on key buses and important signals--greatly simplifies attaching a logic analyzer or oscilloscope.

Getting down to basics

With the correct probe in hand, the designer should first determine the quality of the power and clocks to the ASIC. An unterminated clock, for example, could greatly reduce the quality of the clock signal (see Figure 1). In this case, the designer will need to terminate the clock, probably by manually adding some resistance to the clock path.

Once the power and clocks are checked and found adequate, it's time to see what's going on inside the device. The temptation at this point is to run the ASIC full bore using system code, to see if it works. Although that action is hard to resist (after all, the designer has been waiting for this moment for several months), a quick evaluation of critical signals up front will more than likely save the designer days of frustrating debugging later on in the process.

The first step addresses some signals, usually strobes and control signals, that demand careful evaluation with subnanosecond resolution. The designer should use an oscilloscope--or a high-resolution logic analyzer--to view the critical signals to be sure that their timing isn't pushing up against the specified boundaries (see Figure 2). The second step determines if the microprocessor is communicating properly with the ASIC. Typically, executing some simple function--such as writing to a register in the ASIC and then reading back the result--is sufficient.

Figure 3	Triggering a runt
Built-in runt triggering functions in DSOs, found in advanced logic analyzers, allow the designer to trigger and view runts found through margin testing. Shown is an actual runt pulse along with the trigger setup used to capture it.

The second step requires a logic analyzer, because the interaction between the ASIC and the microprocessor undoubtedly involves a bus that is 16, 32, or even more bits wide. The dozens and sometimes even hundreds of channels supported by a logic analyzer, as opposed to the maximum of four channels on an oscilloscope, make the logic analyzer the tool of choice for examining a processor-controlled ASIC.

However, connecting the dozens and sometimes even hundreds of logic analyzer channels to an ASIC can pose a major challenge. Fortunately, available high-density probe solutions for logic analyzers incorporate a sophisticated mass termination technology to deliver four times as many connections in the same area as traditional square-pin style connectors.

These high-density solutions also offer outstanding electrical characteristics for superior DC and AC loading of high-speed signals. Their capacitance is a mere 2 pF, compared with the usual 5 to 8 pF, with a controlled impedance environment to minimize reflections. They also provide complete isolation between channels and shielding to prevent outside interference. To ensure easy connection and to minimize errors when attaching possibly hundreds of connections, many designers prefer to build high-density connectors into their test systems that support those high-density probe solutions.

With all the critical signals evaluated, now is the moment the designer has labored toward for months. It's time to run the ASIC at full system speed and see if it functions.

The moment of truth

The designer can now use system software to exercise the ASIC in depth. External test and measurement tools, such as the logic analyzer and oscilloscope, aren't necessary at this point, because the designer can retrieve all the pertinent information from the system software. Here, the designer should be concentrating on uncovering any design flaws that might be lurking in the ASIC. But remember, a latent manufacturing flaw may still appear at that stage, so the designer must be on the lookout for both.

Once everything is executing correctly and outputting information as it should, it's time to use a logic analyzer to evaluate the bus between external memory and the ASIC. The primary focus at this point is to determine if the ASIC meets setup and hold requirements--one of the most crucial synchronous timing parameters for this type of design. In newer microprocessor designs, the address is often pipelined--that is, an address for the next access appears before the data for the first address is available. So it's important that the designer be able to carefully examine the interactions among address, data, and control lines.

The large number of signals being viewed compels the designer to use a logic analyzer for this usually tedious, time-consuming step. Fortunately, some of the newer logic analyzers can directly trigger on violations of the setup and hold time, dramatically streamlining that stage in the evaluation. An internal setup and hold checker detects transitions in the input signals after they are acquired by the logic analyzer's high-speed digital sampler. The transitions are then adjusted for skew, and violations are flagged if the transitions lie within the interval defined by the designer.

When all is running smoothly and no fatal manufacturing or design flaws have been uncovered, the final step is to characterize the performance of the device.

Traditionally, the designer would rely on an oscilloscope in tandem with a logic analyzer to characterize the ASIC, but using two instruments has its drawbacks. For instance, they must be carefully synchronized. Moreover, the designer must hook up two sets of probes--a challenge with today's high-density designs. To eliminate the complexity of using two instruments, the designer has two choices: to use a logic analyzer that includes an oscilloscope module, thereby eliminating the need to correlate the two; or to use a new type of logic analyzer that supports subnanosecond timing resolution, allowing the designer to perform full ASIC characterization with just one instrument. Whatever test and measurement tools are used, the designer should evaluate the margins of the ASIC and then characterize its clock performance, data and address bus timing, and the performance of asynchronous inputs.

Margin testing

First, margin testing assesses the quality of the ASIC's functions. Typically the margins for most ASICs are somewhat generous to ensure high yields during production. So examining most of the interactions on the ASIC using a logic analyzer should be acceptable. All of the signals would then be displayed together, giving a complete view of the ASIC's margins. During margin testing, it's not unusual to have several bits fail in a sequence, more than likely because of a runt pulse generated when pushing the ASIC to its limits. When that condition occurs, the designer should rely on built-in runt triggering functions in the logic analyzer's oscilloscope to trigger on and view the problem (see Figure 3).

With the margin testing completed, the designer should directly verify the ASIC design against detailed timing simulations, viewing the timing of clocks as well as data and address signals with respect to each other and to asynchronous inputs. In high-speed logic design, clock signal quality is a foremost concern. The designer should acquire the clock signals with sufficient detail for characterizing signal parameters such as clock pulse width and duty cycle. Next, the designer should exhaustively examine the performance of the data bus that connects to the ASIC, including the timing of the data bus accesses relative to the memory and ASIC.

Address timing is an important yet easily overlooked element of ASIC characterization. If address values become valid later than expected, the memory devices or peripherals may not have sufficient address setup time. The detection process can be especially complex when more than one device--such as a DMA controller or a second processor--can drive the address bus. In addition, any asynchronous inputs, such as interrupts, must be measured and their timing characterized with reference to the system clock.

The last task is to characterize the ASIC design at the extreme corners--at low voltage and high temperature and at high voltage and low temperature, for instance. That characterization gives the designer an idea of how well the circuitry accommodates component and temperature variations. Stressing voltage and temperature beyond specified operating conditions can take process variations into account. Stressing, though, must lie within the nondestructive range of the ASIC.

Using the right oscilloscope and logic analyzer, and following the straightforward approach described here, the designer can quickly bring up, thoroughly assess, and characterize a prototype ASIC. Of course, the recommendations above are only general guidelines; each designer must tailor them to the ASIC's specific needs and requirements. In any case, adopting a methodical approach can greatly help streamline the overall process of bringing up an ASIC.

Kenneth Ngoc Nguyen is a hardware design engineer for the Measurement Business Division of Tektronix, Inc., in Beaverton, Ore. He has been with the division for seven years, primarily as an ASIC designer.

James M. Fenton is a senior hardware design engineer at Tektronix. Most recently he has been working on logic analyzer application development in the form of microprocessor, bus, and communications support. In the past, he has held both project leadership and design engineering positions.

To voice an opinion on this or any Integrated System Design article, please email your message to miker@isdmag.com.

integrated system design  December 1998