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What Really Happened at DAC? At this year's DAC, verification was the topic of the day. The conference also saw numerous new start-ups and advances on several fronts. by Steven E. Schulz

The 1998 Design Automation Conference was one of the best in the last 10 years. Over 20,000 total attendees saw a record number of EDA start-ups. Many of them expected the conference to be the "IP DAC," but that notion turned out to be somewhere between hope and hype. No, this year's DAC was clearly about verification, plain and simple. Synthesis and physical design, hardware/software codesign, and EDA interoperability, though, also made good progress.

Quickturn's new Mercury emulation system stole the show. Mercury, which uses parallel-processing PowerPC CPUs, emulates up to 10 million gates, accelerating any mix of behavioral-, register transfer-, or gate-level HDL code along with C software programs for accelerated co-verification. Its Simserver environment compiles event-driven simulation scheduling into FPGA hardware several orders of magnitude faster than software-based simulators. It provides 100 percent visibility into all design nodes, including complex memory configurations. Mercury can also simulate asynchronous design styles, and it supports cosimulation with software simulators.

On a smaller scale, start-up Axis Systems is introducing a plug-in adapter card for Sun workstations that features a parallel architecture of reconfigurable computing elements. A systolic array structure communicates between nearest neighbors to deliver simulations running at hardware speeds.

Many new formal verification products entered the market, particularly equivalence checkers. Most of the tools appear to be quite similar in overall capability, focusing on improved usability and diagnostics. Cadence introduced Affirma, an EC tightly coupled with its line of mixed-language and mixed-cycle, event simulation tools. Like Synopsys in its Formality product, Cadence features common user interfaces and multiple solver algorithms. Verplex's logic equivalence checker (LEC) features special technology to efficiently map differences in state encoding between two designs, and to perform that task rapidly using less memory so it can support larger capacities. Fujitsu/ICL introduced an equivalence checker that it claims to have used internally for several years. Formalized Design announced both an equivalence checker and a model checker. The company touts its LEQ equivalence checker as able to handle 32-bit multipliers and 10 to 20 times more logic than competing tools, as it's not based on BDDs. MC-Check uses a proprietary language (Property Assistant) to specify expressions for model checking.

As for other types of verification, 0-In Design Automation demonstrated formal RTL analysis techniques to facilitate "white-box" verification. Nonintrusive checkers help the tool identify corner cases not easily found using other test vector generation techniques. Verisity employs its own language to specify simulation tests at higher levels of abstraction, then analyzes the simulation results with a rich set of diagnostic tools. System Science introduced Vera-SV, a similar environment for higher abstraction simulation control that supports coverification of hardware and software. In it, all objects have full timing capability and support true concurrent testing for shared resources.

This year's DAC was also important because we're finally beginning to see the merging of synthesis and physical design. Ambit and Synopsys are moving in that direction at an algorithmic level, and Avanti is providing tighter linkages with physical design. Each company has a unique view of how to couple synthesis, floorplanning, and placement, so it'll be exciting to see how this plays out in the marketplace. Keep a close eye on Monterey Design Systems. It hasn't announced products yet, but it's striving for the theoretically perfect approach for advanced silicon physical design.

In floorplanning, Aristo Technology offers a new alternative emphasizing presynthesis block-level topology and interconnect. Each block may represent RTL, memory, analog, or a collection of subblocks. I was impressed with the company's comprehension of process information, metal levels, gridless detailed routing, support of partial, incremental constraints, and automatic block creation from imported LEF and PDEF. It manages aspect ratios and pin placement, and it auto-generates portfolios of potential solutions at each level of refinement, based upon user-defined scenarios. Not to be outdone, Tera Systems offers yet another approach that integrates automatic partitioning of control and datapath portions of RTL designs with block-level floorplanning for optimized area and speed. When coupled with additional supporting methodologies, it's a good vehicle to support RTL sign-off capabilities. Another start-up, Everest Design Automation, will be offering its own structured floorplanning and gridless routing environment that focuses on interconnect design.

It was also a very good year for interoperability standards. Synopsys announced the open licensing of its widely used synthesis design constraints format. Though that event may create some friction with the existing IEEE Design Constraints Working Group, in the end I believe both parties offer unique value. Synopsys emphasizes timing, whereas the DCWG covers a broader scope; I propose, then, that both sides discuss a merged solution.

Also at DAC, Cadence announced plans to release the LEF and DEF physical constraints formats in the form of procedural interfaces. The hope is that a singular and consistent interface can address the existing multiple file format versions. Cadence also surprised many by announcing their intention to support OLA, which includes the all-important DCL and DPC procedural interfaces (now being standardized through IEEE), as well as ALF. Furthermore, a well-attended CHDStd presentation indicated growing interest by EDA vendors in supporting an open, concurrent infrastructure for design. VSIA delivered on several essential specifications, and Mentor Graphics and Synopsys jointly released the Reuse Methodology Manual. I was also very pleased to see that EIA-Japan released its EDA roadmap endorsing the system-level design language (SLDL).

Several panel sessions addressed system-on-a-chip challenges. I moderated the VHDL International panel session entitled "What Will Prevent Us from Implementing Systems on a Chip?" The expert panelists and attendees all agreed that system-level integration is not "just like building a PC board"--it's much harder than most people think. The conclusion was that consolidation is likely and only the most sophisticated companies will do it successfully. At another DAC panel, Richard Newton asked the participants if VSIA standards were sufficiently aiding system-on-a-chip design. Not one panelist concurred. So after three years of IP rhetoric, reality is beginning to set in.

Even so, several companies provided some real surprises. Arexsys demonstrated a hardware/software codesign tool that truly supports flexibility in architectural exploration and partitioning. Users enter graphical SDL, VHDL, and/or C to describe functionality. The tool then automatically inserts communication protocols across channels, generating all necessary control, handshaking, and buffering signals and control blocks. Next, users select one or more blocks to synthesize into clock-accurate RTL VHDL for hardware, or to do task scheduling on those selected blocks for processor execution.

In behavioral synthesis, Meropa is offering a product it claims performs better than Synopsys ' Behavioral Compiler for timing and scheduling. The Mustang data path placement tool from Arcadia offers more sophisticated extraction of complex structures, such as Wallace trees. Ambit is also previewing a new datapath synthesis capability. Everywhere I look, major transformations are occurring in synthesis.

Bits and pieces: The CEO panel held few surprises. EDA vendors politely clarified their own positions, but failed to thoroughly address user issues. Avanti, though not represented on the panel, seemed to understand the emerging silicon problems better than most and now has a focused solution in place. Cadence is also deeply involved in defining their tool solutions. Synopsys , on the other hand, has so far missed the forest for the trees, failing to see that there's more to R&D leadership than financial percentages. Overall, most of the major innovations for retooling EDA are coming from start-ups, whereas the major EDA players offer incremental innovation.

The annual Dataquest forecast briefing validated expectations: The standard-cell SLI market will grow to $30 billion by 2002, with 60 percent of it driven by consumer applications. The briefing cited design methodology, targeted libraries, manufacturing excellence, and system knowledge as key ASIC vendor requirements for SLI success. It noted that of the 15 million gates available at 0.18 µm, we are only using 40 percent, because of the lack of new tools. In addition, our high-end tools will start requiring 64-bit processor architectures to keep pace. Gary Smith stated it best: "EDA tools actually hit the wall at 0.25 µm, not 0.18 µm!"

Smaller bits:
• In the Linux vs. Windows NT battle, it seemed the real conflict was between designers and their management. Linux may be reliable on PC hardware, but so is Solaris--and management needs official support channels. However, it was hard to ignore the number of Windows NT demos.
• EDAC sponsored an investment panel, in which analysts voiced their lack of confidence in fabless IP suppliers. Several panelists commented that few (if any) star IP providers are expected to emerge anytime soon.
• EDA for FPGA is rapidly maturing, and has now arrived with equal respect. Companies like Synplicity and Exemplar are forging new paths that could eventually challenge the ASIC low end, while simultaneously easing a smooth migration path.
• The DAC Silicon Village was not well-attended, because attendees, wanting to learn about new design methodologies and tools, weren't clear about the village's goals.

The EDA industry is clearly addressing verification and timing convergence fears, but the Great White Hope of SLI has yet to materialize. From the looks of things, it may take a few more years.

Contributing Editor Steve Schulz is a senior member of the technical staff in Texas Instruments Inc.'s Worldwide ASIC group in Dallas. He's also the president of the board of directors of VHDL International.

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integrated system design  August 1998