Design Automation

This month, we complete our three-part report on readers' experiences designing circuits implemented with deep-submicron (DSM) processes. We gathered the information from a survey of our readers we conducted last July. The questionnaire examined how they're designing DSM circuits and what new methods they're employing to cope with the special problems such design poses.

In November, we focused on design flow issues (p. 16). December's report covered design verification (p. 20). Here we discuss the final part of the survey--signal analysis and the trend toward the use of ASIC vendors' tools to address the shortcomings found in commercial tools.

We asked our readers what measures they're taking to mitigate the susceptibility of small process geometries to power, electromagnetic interference, crosstalk within and between routing layers, and so on. To evaluate current signal analysis tools on the market, we asked: "There are numerous analysis tools coming on the market to evaluate a layout for power, EMI, reliability, and so on. Have you had any experience with such tools, and have they been essential to completing a deep-submicron design?"

"In general on my designs, we've assigned a physical design specialist to watch for these problems, and to date we've never had difficulties with the final designs," reports B.H., a designer who wishes to remain anonymous. (Initials are used throughout for respondents who asked not to be identified.) "I've seen instances in which designers who don't focus on those issues have problems, often with resistive power paths to clock buffers, causing the designs to run slower than expected."

To illustrate his point, B.H. cites a test his company ran against Powermill from Synopsys , Inc. in Mountain View, Calif. "We estimated power the old-fashioned way--with a spreadsheet and estimates for how many gates were switching at what frequency--and we were within 30 percent of Powermill's results. So the old ways work to an extent."

Nevertheless, he says, "Signal analysis tools will be more crucial as the gate counts keep growing and we run designs at higher frequencies with narrower metal widths."

One issue frequently cited is how to estimate power more accurately. "Accurate power estimates affect both perceived performance and the cost of the ASIC," says Paul Ho, staff design engineer at VLSI Technology, Inc. in Burlington, Mass. "Power estimates dictate derating factors for timing, power, bus sizing for the chip and hence cost, and also packaging, which affects cost tremendously."

Anders Nordstrom, a senior ASIC designer at Northern Telecom Ltd. in Ottawa, points to his experience with Wattwatcher from Senté Inc. in Chelmsford, Mass., which was used at the RT level to get a power estimate. "We have no metric of its usefulness, since the tool can be off by 20 percent or more. We also used Powermill from Synopsys for more power-critical designs, and in those instances we had to have an accurate number; otherwise we may not have had a product."

D.D. says that his team started having signal integrity problems with 0.35-µm processes. Until then, they were able to live without signal analysis tools, but he sees no way of moving forward to 0.25-µm processes without them. "We need an accurate parasitics extractor, a power analyzer, and other tools for future designs."

Implementing designs in 0.25-µm processes, Dan Robbins, a staff engineer in ASIC design engineering at Mitsubishi Semiconductor America in Durham, N.C., says that he has no need for such tools. "We don't currently use them. We have had some power problems due to the high clock speeds we're running--greater than 100 MHz--but we try to minimize them by changing the way the clocking schemes work or the functionality."

Anders Nordstrom of Northern Telecom says that without Powermill, 'we may not have had a product.'

Other respondents, such as Gary McMillian, vice president and chief technology officer at Systems & Processes Engineering Corp. in Austin, Texas, are developing a reliability analysis tool in-house. Writes Raghu Sastry, project lead for HAL Computer Systems, Inc. in Campbell, Calif.: "We have our own in-house tools for power distribution checking, electromigration checking, manufacturability and reliability checking, and clock skew analysis, and they're required for sign-off."

Among commercial tools, the respondents see no complete solutions. "Simplex's and Synopsys /Epic's tools are good," says R.C. "However, neither really has all the tools, so designers often have to mix and match the output of these tools with in-house scripts and tools to make the design flow work."

Rob Maffit, chief technology officer at Prescience in San Carlos, Calif., presents a more pessimistic appraisal of commercial tools. "Frankly, most of them don't merit their effort. They're far from easy to integrate into the design flow, and their results are suspect. They rely on unverified models coded by application engineers anxious to make a sale, not foundry-supported, solid data. Today, the power, reliability, and RF compatibility are whatever you can get that doesn't affect the schedule."

Raghu Sastry of HAL Computer Systems says that his company has proprietary tools for power, clock skew, electromigration, manufacturability, and reliability analysis.

The case for ASIC vendors' tools With the move to deep-submicron processes, the use of ASIC vendors' proprietary tools to access the latest process technology is increasing. Gary Smith, principle analyst for EDA at Dataquest in San Jose, is fond of saying that today's tools are able to create designs for process technology one or two generations behind the state of the art. To take advantage of state-of-the-art process technology therefore, designers have to adopt proprietary tool flows offered by ASIC vendors.

To test this premise, we asked: "Yet another trend that ASIC vendors are claiming is the move away from tool flows and design methods based on commercially available tools to flows based on proprietary tools supplied by the ASIC vendor. IBM Microelectronics is one vendor claiming some success in this arena. One customer it cited as having good success with this approach is Intergraph. The Huntsville, Alabama-based company routinely designs million-gate ASICs with IBM's flow. Have you had similar experiences? Have they been as successful as Intergraph's? If not, can you cite some of the shortcomings you've experienced with this solution?"

Lynn Watson, president of In-System Design in Boise, Idaho, provides the most compelling case for the trend to proprietary tools. "We've used the core set of tools from Lucent Technologies' Microelectronics Group for some time. Similar to IBM's, their proprietary tools do many things that commercial ones do, but they're tailored for Lucent's process and release requirements. Our experiences have been very good with the tools. They guarantee that nothing is missed as part of the release process while actually supplementing commercial test capabilities as well as increasing confidence in the design. If there is any shortcoming, it's with respect to customer support issues--there's no way a proprietary tool will be supported on a par with a commercial tool."

Martin Taylor, chief engineer of Edna Design in Santa Cruz, Calif., describes a similar experience with IBM. "I've used IBM as a vendor, and they do have an impressive in-house tool set and engineering support team. They specialize in very large ASICs and are able to support those designs. Also, their technology is top-of-the-line. They are particularly impressive in their support for test integration, static timing analysis, and clock tree synthesis. They also have their own synthesis tool, called Booledozer."

Nordstrom recounts Nortel's experience with some of IBM's tools. "We used IBM's proprietary static timing analyzer, Einstimer," he says, "but used commercial Verilog and Synopsys synthesis tools instead of IBM's Booledozer synthesizer, since we didn't want to spend the time learning the proprietary tool. IBM is transferring technology contained in Einstimer to Synopsys , and it's being incorporated into Synopsys 's Primetime--a maneuver opposite to the trend you've cited. IBM also has some special tools in the design-for-test arena, but that's mainly because the capabilities don't exist in other tools."

L. N. puts the problem of proprietary tools into perspective. "The IBM internal flow is extremely powerful and is significantly better than anything currently available commercially. The main problem is that the tools aren't designed for the casual user, making them more difficult to learn and use effectively," he says. "For a smaller design in a more mature technology, or with a less experienced team, the industry-standard tool sets may be a better choice."

Doug Warmke, hardware director at Ikos Systems, Inc. in Cupertino, Calif., suggests that the use of ASIC vendors' proprietary tools may become widespread for system-on-a-chip integration, since the methodologies are so much more complex. "Probably," he predicts, "the eventual system-on-a-chip methodology will be a huge hodgepodge of interconnected tools to do different jobs, some internal to ASIC vendors and some commercial."

The case against ASIC vendors' tools However, most respondents tended to disagree that there's a trend toward ASIC vendors' tools. Some even hold that the tools aren't up to the job of DSM design.

Nancy Nettleton of Sun Microsystems says vendors' tools aren't up to the speed and complexity of Sun's designs.

"We're geting widely mixed results from proprietary flows," writes Nancy Nettleton, ASIC design methodology manager at Sun Microsystems, Inc. in Mountain View, Calif. "I don't think the primary difference in these flows is their proprietariness but in the focus the organization has had on complex, deep-submicron design. Most of the vendor-proprietary flows we see aren't ready for the speed and complexity of the designs we're throwing at them. These flows are slow to embrace hierarchy and timing, the two cornerstones of microprocessor design from the early '90s. Instead, they're largely tuned for flat ASIC design, for which delay prediction within 10 to 20 percent is sufficient--and 10 to 20 percent of 100,000 paths leaves a lot of hand-tuning on a designer's plate."

Tony Riccobono, a staff application consultant for Synopsys in Irvine, Calif., is one of those who disagree that there's a trend to use proprietary tools. "All of my customers who use IBM as a fab use Synopsys for synthesis and Verilog for simulation," he writes. The only IBM tools being used are Einstimer for timing and clock tree synthesis and some synthesis with Booledozer."

Riccobono goes on to say: "I'm not sure which ASIC vendors are claiming to move away from tool flows and design methods based on commercially available tools to ones based on their proprietary tools. Like who? IBM, among others, seems to be moving more to supporting commercial tools. They may be retaining internal tools where they see the need, but they're certainly not moving away from commercial tools. It's the same with LSI Logic, VLSI Technology, pretty much everyone else I see. There's no trend here." *

To voice an opinion on this or any Integrated System Design article, please e-mail your message to miker@isdmag.com.

integrated system design  January 1998