Feedback Why bother?

To the Editor:

The cover story in the May issue describing the implementation of a DSP in a complex programmable logic device ["Implementing a DSP in Programmable Logic"] describes an effort that can, with some charity, be considered a Pyrrhic victory. Why anyone would attempt to embed the TMS320C25 --a second-generation TI DSP ( TI is now offering a sixth-generation DSP)--to provide lower performance, higher cost, and higher programming risks is beyond me. Perhaps this exercise in futility is undertaken to gain insights into future designs of obsolete DSP devices.

Anyone who has attempted to travel the programmable logic route to digital signal processing knows that programmable logic wasn't designed for it. As a general-purpose logic resource, the FPGA can be effectively applied to logic operations of variable bit length such as are found in encoders/decoders and bit correlators and to finite state machines (like Viterbi encoders) and as linear sequential networks for pseudorandom noise generators, scramblers, and such. In these applications, the FPGA can compete with the microprocessor (general-purpose or DSP), notwithstanding the fact that the interconnect resources consume more silicon than the gates they support.

However, when it comes to the computationally intensive operations that characterize the key DSP algorithms, the path to success is more perilous. For example, an array multiplier that is 16 x 16 or larger consumes an inordinate amount of silicon area and offers performance well below that of a $4 DSP chip. Furthermore, as Martin Langhammer realizes, speed enhancements through pipelining produce undesirable latency that slows down the execution of recursive algorithms.

A better approach to doing DSP with programmable logic is to embed a programmable controller for logic, timing, and data flow control functions, along with a set of compute-intensive processing nodes or cores. Coincidentally, in the same issue your Focus Report lists the DSP cores available on the Altera Flex 10K.

Distributed arithmetic techniques can provide very gate-efficient, compilable, and reusable hardware nodes. Now it would be possible to map signal flow graphs directly into hardware nodes rather than time-shared subroutines serving a single array multiplier. It would thus be possible to realize higher performance at lower power levels and at reasonable costs. Indeed, a high-gate-count FPGA that includes block and distributed RAM, such as the Xilinx Virtex family, may be a suitable candidate for first-generation system-on-a-chip solutions, with an embedded programmable controller core handling all the soft functions usually assumed by a DSP.

Les Mintzer

Consultant
Momentum Data Systems
Santa Ana, Calif.

Martin Langhammer replies:
I think Les missed the point of the article. The design of a TMS320C25 for programmable logic was not meant to imply that it was an ideal solution to replace standard DSP chips, but rather to give a known benchmark to measure programmable-logic-specific processors against. That being said, programmable logic does have advantages for designs, including on-board processors; by adding functional blocks such as GF operators, the programmable-logic DSP would be able to outperform fifth-generation DSPs for certain tasks. In addition, a PLD system-on-a chip design incorporating a processor has one definite advantage over ASICs--unlimited reprogrammability, which will allow you to debug your hardware in real time, rather than in a software simulation.

I've also designed several programmable-logic-specific processor cores, both CISC and RISC. Rather than following a known architecture, they were designed specifically to allow the user to specify as much of the architecture as possible. With the CISC processor, even the instruction set is defined by the user, as well as the bit width, number of registers, number of interrupts, and so on. (It is available for free on my Web site, http://www.hammercores.com.) For one RISC processor that I designed, the instruction set and the datapath size are fixed, but the user can set any number of registers, any number of I/O ports, and many other features--and it routes to over 50 MIPS as a soft core and has a single-cycle multiplier-accumulator (16 x 16) as well.

As Les states, certain signal processing functions are well suited to PLDs, and I've implemented these as well. But today's programmable logic can support a lot more than what Les has listed. I also have a Reed-Solomon compiler that will generate encoders and decoders for virtually any valid RS code, operating at up to 400 Mbits/s, again as a soft macro, and many more circuits.

I disagree with Les about 16x16 multipliers being too ungainly in programmable logic. The latest parameterized Altera multiplier (software V9.0) operates at over 100 MHz in 430 LCs--high performance and cheap. While distributed arithmetic can build some efficient high-performance structures, the technique is limited to applications where one set of inputs to a vector is fixed, such as FIR filters and DFTs. Many signal processing applications use continuously varying data, such as equalization. Sometimes, integer math just doesn't work, as in coding theory applications, where finite fields are used.

As a final note, I would encourage Les to have a more enthusiastic look at PLDs. They're useful for so many more things than just distributed-arithmetic FIR filters!

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integrated system design  August 1998