design tools

Building Robust, Reliable Nanometer ICs By performing both timing analysis and activity analysis early in the design cycle, Texas Instruments developed a methodology that successfully addressed the problem of characterizing a custom block used in a set-top box processor. by Paul Wiley, Linda Hurd, K. S. V. Gopalarao, and Nitin Deo

As nanometer technologies continue to advance, the complexities of system-on-a-chip designs are moving toward 30 million to 40 million transistors with extremely complex interconnects. Such designs are making yesterday's methodologies ineffective and call for major retooling. Because ASIC and custom designs are converging in system-on-a-chip designs, the engineering community needs to leverage the tools and technologies used in highly complex structured custom ICs, such as DSPs and microprocessors, in their ASIC and custom design flows.

Complex nanometer designs can show how designers use the best-in-class tools to analyze a single dimension of their design. Yet they can also prove that without integrated and cohesive methodologies, point tools may not be deployed correctly to identify the right problem at the right time in the design flow.

In nanometer design, the goal is to develop an IC that's robust from the perspective of timing and power, as well as reliable, having a clean supply voltage built for electromigration (EM) tolerance (see "The Nanometer Design Pyramid"). The design team at Texas Instruments paid attention to those factors when designing a new DSP core, incorporating timing and power analysis tools into the postlayout design flow. To achieve the highly accurate timing data needed for the design, the team used the Pathmill timing analyzer. To obtain full characterization of the average and peak power requirements, the team used Powermill. Finally, the team optimized the design for protection against voltage (IR) drop and EM, using Railmill to guarantee that the design met the EM guidelines specified by the nanometer technology. By performing such careful extraction and evaluation of interconnect parasitics, designers can characterize the performance of individual blocks and thus reuse them in other designs.

Accurate timing characterization
Frequently, custom blocks are embedded in synthesis-based designs to achieve performance, area, and power requirements. Timing characterization of the custom block is required to produce a timing model for the synthesis flow. Typically, such a characterization is performed by running a few vectors with Spice and extrapolating the results to the whole block. VLSI designs frequently include blocks of logic that have been designed using full-custom techniques, and designers often use such blocks to achieve performance, area, and power requirements not feasible with synthesis techniques. The use of custom blocks also makes it possible to reuse existing design blocks whose functionality, area, and performance have been proven.

The characterization of a custom block with respect to timing requires several components, collectively referred to as the timing model of the block. Although the formats vary greatly depending on the synthesis or timing tool reading the timing model, the components included in timing models are fairly standard (see the table).

Several techniques can be used to compute timing models, including exhaustive circuit simulation, limited circuit simulation, and timing analysis. To achieve the highly accurate data needed for nanometer designs, the team chose Pathmill because of its ability to perform MOSFET-level static timing analysis and numerical solution techniques to produce accurate estimates of delays. In addition, because they planned to synthesize the bulk of the design with Synopsys Design Compiler, it was important to use a tool that builds timing models in the Synopsys timing model format.

The timing characterization in Pathmill is based on path tracing. Designers must ensure the validity of the paths before they proceed to model building. The validation is more complicated at the MOSFET level than at the gate level, because there are several ways to combine CMOS transistors to form logic gates. Pathmill recognizes and correctly deals with many of those situations. For example, using it with static CMOS gates is almost completely automatic. The tool doesn't, however, automatically handle such logic design styles as pass-gate logic. When the tool doesn't recognize how a MOSFET is used, it makes conservative assumptions, which typically result in very long delays. Designers should examine those long delays and, where appropriate, issue Pathmill commands to let the tool know how the MOSFETs are used. The TI design team referred to that activity as "guiding" the tool (see Figure 1).

Figure 1	"Guiding" Pathmill
By pulling down nmos1 using the command pulldown nmos1 , the user can guide Pathmill to identify the correct long path.

In the example of the circuit shown in Figure 1, Pathmill identified the longest path from b falling to y falling as going through nmos1 with a rising transition. The rising transition through an NMOS device produced a long delay. The path should have really gone through the transmission gate formed by nmos2 and pmos2 . The problem was corrected by issuing the Pathmill command pulldown nmos1 , which tells Pathmill to only search for falling transitions through nmos1 .

Pathmill's effectiveness can be enhanced by following certain design practices. For example, designers can specify all known transistor directions, use a hierarchical netlist, and back-annotate extracted parasitics and device parameters to the original hierarchical netlist. Designers can back-annotate lumped capacitances by using the node_capacitance command, specifying a full hierarchical net name, or they can include the net capacitances with full hierarchical net names as part of the design netlist if they use the Spice format. Distributed parasitics can be back-annotated by formatting them in SPF format and reading them with the -ncspf argument.

The successful completion of the project has had two consequences. First, TI will use the timing model computed for the multiplier in future revisions of the project. Second, several design teams are thinking about incorporating Pathmill into their projects' design flows to characterize custom logic. As an added benefit, the work on characterizing the multiplier also identified several undersized PMOS transistors. The problem didn't cause a functional or timing failure, but it did escape all prior design verification efforts.

Power: A new dimension
Today's high-frequency, complex nanometer ICs require full characterization of the average and peak power requirements of each circuit to support production testing screens; IC package design requirements; and such board-level design requirements as voltage regulator selection, thermal management issues, and decoupling capacitor selection.

In analyzing the power dissipation of a high-performance DSP, the team's primary goal was to gain insight into the average-current characteristics for a range of CPU activities. They investigated the average-current components for each of the individual CPU subblocks and the effect of instruction parallelism on the CPU average current (see Figure 2).

The team used a hierarchical TI-Spice netlist containing extracted capacitance for the Powermill simulations. The technology file was generated by TI using Spice transistor models for nominal process, room temperature, and nominal power supply voltage.

Powermill was a critical part of the CPU power characterization. The average-current histogram files and instantaneous-current waveforms generated by the Powermill simulations provided the information the team needed to understand and quantify primary and secondary components of the total CPU average current characteristics. The work also provided a strong foundation for extending the power analysis from the CPU level to the full-chip level. All of the test cases, with exception of the instruction parallelism test case, were used to take full-chip silicon measurements.

Further detailed analysis of Powermill data resulted in the team's ability to develop an accurate high-level CPU power model and a set of steps for optimizing assembly code with respect to power dissipation.

Robust and reliable design
Designers also need to protect their designs against voltage drop. When designing an embedded core, they have to take extra care to analyze and optimize complex, high-performance custom blocks and then specify guidelines for the usage of that IP block (see Figure 3).

Figure 2	Power simulation
The automated flow developed for running Powermill on the module-level CPU included QuickVHDL, Design Compiler, and Vtran.

TI designed a high-performance DSP as a core, which was expected to be used in high-performance, high-volume DSP-based ASICs for data communications, telecommunications, and Internet service provider applications. Owing to the wide range of applications for the core, it was especially important that the designers be able to ensure reliability. The team used Railmill, and the reliability analysis revealed several potential problems with the power grid design for the DSP core that were easily fixed with optimizations. For the team, that confirmed that if reliability analysis is done early in the design cycle, it helps increase the quality of the design.

Figure 3	Flow for EM and IR drop analysis
The tool flow used to characterize the custom blocks, which includes tight integration between Railmill and Chip Viewer, is now established and documented and can be used by other design groups.

Since the logic for the full chip was unknown (the function, complexity, and so on), testing had to ensure that the power bus was robust enough to handle different current density requirements. The challenge was to analyze the core design thoroughly enough to guarantee its reliability for both high-speed performance and high-volume production. Those requirements called for transistor-level analysis, and it was critical to check for EM to ensure the long-term reliability and performance of a DSP core that would support high-volume production.

Reliability analysis and optimization
At every step in the design flow, the DSP team analyzed reliability, along with function, timing, power, and physical implementation. Every time there was a new physical design, the team learned things about the timing and power as well as about IR drop and EM. By identifying reliability problems early in the design cycle, they realized significant cost savings and avoided difficult and time-consuming fixes.

The team designed each hierarchical block with certain assumptions regarding the power grid available to that block from the core level. First, they analyzed the blocks for timing, power, IR drop, and power net EM to guarantee their performance and reliability. Then, they assembled the core and performed the same type of analysis at the core level, thereby using a bottom-up hierarchical approach. Although the block-level design was robust, analysis done at the core level enhanced the overall reliability.

To avoid problems with the final product, designers need to provide strict guidelines regarding the use of their core. Such guidelines typically include the definition of a power ring around the core, specifying its width, as well as the number of taps from the ring into the requirements of the complete core. The team's thorough analysis methodology ensured the quality of the guidelines.

Analysis of EM and IR drop for the core design involves four stages: extraction, netlist generation, scaling for target frequency of operation, and simulation. The team extracted parasitic resistance of the power network and capacitance of the signal network using TI's internal extraction tool. The parasitic data represented the true worst-case condition for EM and IR drop.

The team performed separate Railmill runs for each analysis, applying different conditions depending on the type of analysis. It's advisable to analyze the most stressful conditions for the specific type of analysis and to use different transistor, voltage, and temperature conditions for the respective EM and IR analyses. For EM analysis, the designers analyzed all three current limits: peak, absolute average, and RMS. They assumed a strong transistor process condition for EM analysis, because it represents the most stressful condition for EM. A strong transistor has higher drive capability, and therefore current sourcing and sinking are at their worst. They analyzed each of the three current limits at 1.95 V and 105°C. Finally, they performed IR drop analysis to determine the maximum voltage drop limit on a nominal transistor at 1.71 V and 125°C.

The team rectified EM violations by adding additional vias to reduce the stress on any one via or increased the width of the power lines to take care of the current density in the line itself. IR drop violations were fixed by adding taps to the higher-level metal. In many cases, additional vias helped reduce the IR drop problem, confirming that, in order for a design to be robust, it's necessary to perform analysis at the block level as well as the top level.

Every design has different analysis requirements for detailed issues, such as IR drop and EM. Because of the very stringent requirements for the quality assurance standards of TI's DSP products, it was absolutely essential to develop an analysis methodology that could then be used by other design groups. The entire project required several months of effort and resources from design engineering, as well as software engineering and EPIC's technical staff. However, the benefits of the effort are evident in two ways: The team developed a highly reliable DSP core, and it established a complete methodology that's now easily adopted for other designs.

Paul Wiley is a member of the technical staff in the DSP organization at Texas Instruments, Inc. in Dallas. Currently, he's a member of a design team responsible for timing verification, interaction with external and internal EDA organizations, and development of custom EDA tools for the design of high-performance DSPs.

Linda L. Hurd is a DSP applications engineer and member of the group technical staff in the DSP new business development group at TI in Stafford, Texas. She has worked in the semiconductor industry for over 14 years and has been with TI for 7 years.

K. S. V. Gopalarao is the reliability CAD program manager at TI's ASIC Division in Dallas. He's responsible for CAD tools in such areas of reliability as electromigration, ESD, and antenna effects.

Nitin Deo is a physical verification product specialist at Synopsys , Inc. in Mountain View, Calif., and is responsible for extraction, reliability, and characterization technologies for its Epic Technology Group. For the past 15 years, he has performed various design, application, and product management roles in ASIC and EDA design.

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integrated system design  August 1998