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IC Density Drives Array Packages To keep up with the growing number of I/Os on ICs, designers are turning to array attachment and new approaches to packaging. by Doug Trobough

It seems that there's no end in sight. Just as soon as a 1,500-I/O design appears on the horizon, a 2,000-I/O chip is planned to follow. That raises an important question: How is the rapid increase in I/Os affecting chip carriers and the boards on which they're mounted?

The most important change to silicon in response to the increase in I/Os has been the gradual use of area attachment over peripheral wire bonding. Area array has also had a large impact on the packaging industry. Prior to those shifts, the packaging industry's design approach was to use fanouts (see Figure 1): the I/Os were on the perimeter and fanned out until the pitch was large enough for the chip package and PCB to handle it. Also, array packages require large amounts of routing between I/O pads, changing completely the designers' approach to the package.

The rapid increase in IC I/O density is outpacing the interconnect industry as a whole, and the capability gap it's creating is a growing concern among IC manufacturers and system OEMs. There is good news, however. Cooperation among companies in the electronic supply network is being fostered at higher levels than in the past. In addition, the U.S. government, in the form of the National Institute of Standards and Technology (NIST), has recognized the technology gap and is planning to fund research in that area. Other organizations are also doing research into the matter. Now more then ever in electronic packaging, long-term success will depend on planning, communication, and partnerships.

The shift to array attachment
Why did the shift to silicon array attachment and plastic array packages occur? The principal reason is the combination of high I/O density and distributed power and ground.

The great increase in the I/O density of silicon and therefore of silicon packages occurred for two major reasons. The first is the rapid rise in the average number of transistors on ICs, which also leads to distributed power and ground connections, and the second is the growth of bus width. The increased number of transistors has had several effects on silicon, including more layers of aluminum wiring. The increased density of the aluminum wiring has, in turn, reduced the current-carrying capacity in the wires, causing more power and ground connections to be spread over the surface of the silicon. The additional power and ground connections work best when located near the part of the IC to which they're supplying power, leading to a higher number of I/Os and area connections. The growing bus width has significantly raised the number of data and control lines required on an IC. Additionally, the increased number of I/Os now exceeds the peripheral bonding pad capability on some ICs, which is particularly troublesome when die shrinks are being considered.

Power distribution is itself a significant issue. Higher frequencies, lower voltages, higher current draw--all have combined to change the designers' approach to power needs. Not only has the combination forced some designers into using array attachment, but it has also affected the full distribution path. The high inductance in the power supply and ground return path is the major force behind the change. High inductance causes a current time delay at switching, slowing the rise time of the signal. It can also contribute to ground bounce, in which the ground plane voltage moves away from 0 V during switching. Together, the two effects increase noise in the system and decrease the timing available for determining signal status. Array packages can be significantly lower in inductance than QFP-style packages, and technology improvements are under way to reduce inductance (or the effect of inductance) on motherboards.

There are other reasons for the trend to array packages, too, such as the large size of peripheral leaded packages (PQFPs), the affect of the inductance of surface-mount technology leads on high-frequency ICs, EMI noise, assembly issues for very fine pitch QFPs, and the cost and electrical performance of ceramic packages.

When the I/O exceeds 200 to 250 pins, PBGAs displace PQFPs. The size difference and the reduced surface-mount assembly yields become large enough to overcome any cost difference that remains between the package types. CBGAs still play a significant role in the packaging industry, but there's pressure to continue the move to plastic. The dielectric constant for the ceramic packages is near 10, which lowers signal propagation speed by about 50 percent. The conductors on those packages are typically sintered tungsten, which has low electrical conductivity compared with copper. Ceramic packages currently also have advantages in thermal conductivity and in their high-I/O flip-chip packaging.

Package design rules
How does a designer convert those array requirements into the design rules for the package? The following is a summary of the key design parameters, as well as an example of the design rules, for some packages meeting the requirements of the 1997 edition of the Semiconductor Industry Association's National Technology Roadmap for Semiconductors.

Figure 1	Low-I/O CSP flip-chip bonding
This design for a flip-chip chip-scale package (CSP) fans in from bonding pads having a 200-µm pitch; array pads on the opposite side have a 0.5-mm pitch. Higher I/O counts require arrays of flip-chip pads.

Most of the parameters discussed below are classic requirements for determining routing density on a package. The numerical values of those parameters and how they're combined form the crux of the density issue. By understanding the interaction of the values, a chip package designer (or fabricator) can determine the design feature requirements:

• The number of I/Os. The number of I/Os is not a strong driver in itself, but in combination with die size and planned die shrinks, it contributes to the importance of the other factors.

• The number of rows. The number of rows determines the maximum number of traces to be routed in the free spaces between pads. The effective number of rows, combined with array pitch, primarily determines feature size.

• The array pitch. Combined with the number of rows, the array pitch is the most important factor in determining the number of layers and the feature sizes required to produce a design. The most important characteristic is the open space between pads, which allows the escape routing of internal rows of pads.

• The shape of the array (full, open center, and so on). The most important aspect of the shape of the array is the die's own internal free routing space. In a full array, all of the IC pads need to be fanned out, maximizing the impact of the number of rows. In an open center array, there's room available to fan in some of the I/Os, reducing the effective number of rows for routing.

• The location of power and ground connections. If the power and ground pins in a full array are segregated in the center of the design, the routing from them can be made with fewer connections. That effectively reduces the number of rows of pads for routing. If the power and ground pins are interspersed asymmetrically, it may result in localized density that keeps the effective number of rows high, because areas of the chip require full routing. Localized density is a potentially critical issue and needs to be considered as part of the chip pin layout.

• IC pad layout styles. Most arrays are set out in grids, which are easy to design and describe. They are not, however, the most efficient method of high-density routing. Basically, grids end up setting the design rules according to the requirements of the IC's centermost I/Os. There are alternate-array patterns, which if properly executed, permit greater surface area for routing. One example is the "clamshell" design method, which has a scalloped edge pattern that appears lobed. Alternate arrays increase access to internal sections of I/Os, effectively reducing the number of rows of pads.

• The package size and grid. The final chip package size and grid also have an influence on the routability of the package. Routing all I/Os outside the silicon outline maximizes the effective number of rows of pads. You may have to study the package to determine if it's a good fit for the design. Although one might assume that a smaller package is more complex to design, that isn't always the case.

• The required electrical performance. Rising operating frequencies require power and ground planes that provide reference for signal traces, power distribution, and crosstalk and noise reduction. That adds to the layer count and, to a lesser extent, the routing density of the package.

Packaging costs
What do all of those mean for the overall package? Essentially, three categories drive packaging costs: material costs, process costs, and yield. Because material costs are relatively small and fixed by part size, process costs and yield are the true main factors. Process costs are driven by the number of units produced from a given amount of input.

The size of the product (actually the number of parts per panel) and the required number of process steps also affect cost. Microvia build-up technologies, which are the most common density solution for demanding boards, have a large number of process steps associated with each layer of microvias, or high-density interconnects (HDIs). Thus minimizing part size and the number of microvia layers helps control cost.

Quality depends on defect density, opportunities for bad holes, and sequential yield loss. The board products have very fine features, resulting in higher defect densities than standard products, so minimizing the area of fine features will improve yield. Hole formation defects are based on a per unit basis; therefore the rate will be related to the total hole count. Sequential yield loss is a characteristic of the build-up microvia process. The yield loss from the first microvia process is cumulative through the second process. In other words, the yields for both steps multiply to achieve the final yield. Standard multilayer board processing allows for inspection of the layers before final lamination and removal of the defective product. Minimizing the number of build-up layers, therefore, is an effective strategy for improving yield and achieving cost advantages.

A good model for a high-density package is to target a total of four layers, with two microvia build-up layers on the chip side. If designers assume that type of construction, they need to observe the appropriate design rules to meet the SIA roadmap's requirements (see the table).

Production challenges
With such small geometries for leading-edge ICs, cost-effective packages are very difficult for the plastic package industry to produce. The current standard package has lines and spaces in the 75- to 100-µm range, with the best in production at about 38 µm. Production challenges have limited the supply and have raised considerable concern among the high-end silicon suppliers, leading to a joint program between the Interconnect Technology Research Institute (ITRI) and Sematech to bring North American suppliers up to speed on the package requirements. A NIST/Advanced Technology Program focus group on electronics is also addressing those package types.

The base board technology is affected in much the same way as packages, with I/Os per unit area acting as the key driver. The increasingly large and dense array devices are pushing circuit boards beyond the limits of conventional PCB technology. Layer counts for high-end boards have grown dramatically in the last year, followed by a dramatic increase in blind and buried via constructions (see Figure 2). Blind and buried via boards have conventionally drilled holes that extend only partially through the board. The progression is a natural one, passing through density-enabling technologies and culminating in the use of microvias (see Figure 3).

The emerging requirement for microvias in North America are both interesting and somewhat ironic. HDIs are at the upper end of the board interconnect density range and are dominated by Japanese manufacturers, who use them primarily in consumer products. Asian companies have also led in plastic packaging, mostly because of its low cost. In North America, high-end silicon manufacturers focused on ceramic packaging, while the system designers stayed with conventional PCBs. That's led to dominance by Asian manufacturers in HDI, yet at the same time, the use of HDI technology is enabling North American companies to compete in their areas of strength, high-end silicon and electronic systems.

One area of difference between packages and HDI PCBs is that packages are high-density over most or all of their area, whereas HDI PCBs are generally high-density only in selected areas.

Production in North America
Many issues need to be addressed to produce such packages and PCBs in North America, and they broadly fit into a few categories. In the area of density-enabling technologies, feature size will need to be reduced 70 to 80 percent in the next five years (see the table again). In the PCB industry, the historical time span for a change of that magnitude is 15 to 20 years. Although meeting such a goal is already technically feasible, it's not economically viable. For example, new photoresists are capable of achieving the goal, and photomasks are available (though not widely in large format), but other areas aren't as well developed. Feature formation technologies, such as etching and electroplating, are still designed for much larger features. One of the more promising advances related to circuit formation is the use of copper in IC processing, which has the potential for improving some of the fundamental copper technologies, like field metal deposition and etching.

Figure 2	High-density CSP
The cross section of a high-density CSP shows 75-µm holes. A small hole size is required to route the array.

There are issues in the field of stacked vias as well. Most microvia technologies form vias by making a hole in the outer dielectric layer and metalizing the hole with copper plating. To add an additional layer of microvias, the top pad of the lower via layer is "dog-boned," creating a new pad without a hole in it. The "dog bone" pad takes up valuable routing space, reducing the routing density. Several programs are under way to develop methods that will allow such technology to become commercially viable. Additionally, a few companies have established proprietary technologies for stacked vias.

Figure 3	Interconnect technology progression
Increasing chip and board density drives IC packaging and boards to more complex technologies and processes.

In the area of circuit registration, current material systems and processing equipment fall far short of meeting the positioning requirements of 25- to 50-µm accuracy. It's likely that precision image recognition systems, attached to stepper-type imaging systems, will be required to achieve the necessary accuracy and overcome the material systems' lack of predictability.

Conventional PCBs will eventually have the same requirements, but they tend to lag about 24 months behind packages in density requirements. A significant difference between chip packages and PCBs is size; a large package is about 50 mm ² , whereas a high-density system board can often be several square feet in area. That means that the defect density must be much lower in chip packages to achieve viable yield results.

High-density modules
Another way to deal with the yield issues associated with PCBs is to reduce the area of high density or to decouple it from the PCB. The area of high density can be reduced by using high-density modules to contain most or all of the high-density portions of the electronics. Modules are much smaller than the motherboards to which they're attached and are made with more advanced interconnect technology. Modules enable designers to use a number of design approaches when working with system boards. By using modules, they can put all of the speed-sensitive components tightly together, improving performance. Designers have also used modules to effectively handle rapidly changing component technologies, like microprocessors, without redesigning the system. Another use of modules is the mass customization of systems with reduced design time and manufacturing cost. For modules to be most effective, two conditions need to be met: Cost-effective manufacturing has to be available, and enough density needs to be removed from the motherboard so that it can use conventional technology.

Another method to reduce PCB density is the use of "density patches," which are technologies applied only to the area of the PCB that requires the elevated density. Several methods have been developed. For example, a flexible HDI substrate with a lower density pattern on the back is bonded to a matching pattern on a PCB. The matching pattern is chosen to make it possible for conventional technologies to be used on the PCB.

Other technologies, like improved embedded passive components, are also being developed to help deal with density issues. Removing the discrete passives from the board surface not only reduces component area and assembly complexity, but also can reduce the number of vias in the design and improve the density capability of the technology. Several programs are doing research to improve those technologies, including ITRI, the National Center for Manufacturing Sciences (NCMS), and the National Electronics Manufacturing Initiative (NEMI).

A final area of improvement for both chip packages and HDI PCBs is the creation of alternate building methods, particularly nonsequential (parallel) building processes. The parallel building processes may be similar in approach to the current multilayer ceramic package methods. In an example of that approach, circuit layer pairs are created and z-axis vias are added. Each layer is inspected for quality. Via layers (z-axis connections) are then created and again inspected for quality. Those parts are then laminated together to form a finished package. That type of building method eliminates the cumulative yield issue of sequential builds and allows faster velocity through manufacturing. The capability and economics of such via formation and the registration of the layer pairs will make the technology acceptable. Several versions of the approach have been produced, with the ALIVH (Any Layer Invisible Via Hole) process from Matsushita being the best known version.

Doug Trobough is the director of engineering development for Merix Corp. in Forest Grove, Ore. He has worked in the interconnect industry for 18 years in a number of technical and customer development roles. He has also worked in many segments of the PCB industry, including chip package substrates, flexible circuits, microwave circuits, and high-end conventional circuits.

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integrated system design  August 1998