design flow

The advent of million-gate ICs is driving great changes in the EDA environment, from gate- or register-centric to functional, block-based design. This article, on overall RTL methodology, is the first of a five-part series on issues and trends for the next generation of designs. The other articles will cover physical verification, IP and cores from the perspective of the Virtual Socket Interface Alliance and Silicon Integration Initiative's ASIC Council, the requirements for next-generation design languages, and testing deeply embedded system-on-a-chip ICs.

Don't look now, but a complete retooling of EDA is almost upon us. On one side, silicon capacities are coming at us with nasty quantum physics problems that just won't yield to our old, familiar flows. On the other side, those capacities are allowing unprecedented levels of system complexity, opening new markets that promise to keep the electronics industry growing at enviable rates. Yet at the same time, ASIC suppliers are setting their sights on a new RTL sign-off to meet increasing market pressures.

Managing such system complexity in a design flow requires new perspectives and paradigms, and EDA tools must respond to support larger, more complex designs in less time, with early confidence that product requirements and expectations will be met the first time. Responding to this increased complexity isn't just a goal; it's a mandate that calls for the "RTL virtual prototype," a methodology focused on achieving working silicon for complex designs within tight schedules by allowing designers to perform RTL analysis, synthesis, and verification. However, a shortage of appropriate tools limits our potential to reap the benefits of RTL design. We must work with EDA vendors to develop interoperability standards that allow us to take advantage of tools that support the methodology.

The problem

The increasing complexity of system design is making it necessary for designers to exploit several key dimensions in their designs. First and foremost, they must raise their level of abstraction in analysis, and to do that they must move much of the silicon-sensitive analysis functions from the postlayout design stage up to the logical design space. Silicon-sensitive analysis includes far more than timing concerns. Power, metal migration, voltage drop, crosstalk, and functional faults due to physical design decisions are becoming every bit as important to a product's time to market (and time to profit).

Second, designers must take advantage of the intrinsic hierarchy in designs and leverage more modular and incremental bite-sized chunks for analysis. It's rarely reasonable to expect analysis tools to work with the entire design to draw conclusions about it; however, a tool's ability to do so is important, especially when analysis requires knowledge extracted from both the logical and physical design hierarchies, which are often different. Overestimating, or "guardbanding," can be used during the early stages of the design, but most current tools don't even attempt to compose an analysis of the entire design from multiple runs on hierarchical fragments.

Until now, RTL analysis has suffered from gross inaccuracies, since mapping to physical library elements hasn't occurred yet. Estimation tools are notorious for error rates of 50 to 100 percent or more, whereas many experts agree that accuracies of within 15 percent of Spice are necessary for widespread practical value. The problem is that physical design has always lagged behind RTL analysis, creating a chicken-and-egg scenario. Even if RTL analysis tools were adapted to consider physical design implications, the information just isn't available until much farther downstream, when it's too late.

Nevertheless, the new RTL analysis methodology will be crucial to developing the RTL virtual prototype, which is important for several reasons. First, the virtual prototype responds to the growing design complexity that threatens to overwhelm analyses performed at lower abstraction levels, making such large designs otherwise impractical. Second, it will facilitate widespread adoption of design reuse at the RT level, already recognized as a requirement by industry groups such as VSIA (Virtual Socket Interface Alliance) and RAPID (Reusable Application-Specific Intellectual Property Developers). Third, it will permit faster iterations of design trade-offs, leading to more rapid prototyping and design development to keep up with time-to-market pressures and shrinking product life cycles. Taken together, these reasons form a very compelling argument for the RTL methodology and tool set, despite the obstacles that must be overcome.

As the system-on-a-chip era rushes in, promising greater business opportunities for 1998, the lack of tools for the necessary RTL methodology becomes obvious, and time is running out.

The solution: A new RTL methodology

The new RTL methodology is an entire philosophy focused on achieving working silicon for complex designs within worrisome time-to-market constraints. It leverages the latest EDA technologies (including several that are still emerging) but, more importantly, mandates a definite shift in design abstraction for analysis. Although most designers already use an RTL methodology for design entry and functional simulation, the new RTL analysis methodology is substantially different.

	The new RTL analysis methodology
The RTL analysis methodology, which consists of five major components, will require new design flows and greater interaction among tools. (Visualization is a possible capability for the RTL virtual prototype.)

The new methodology comprises five components (see the figure):

• a high-level design entry environment
• an early RTL design and functional verification environment
• complete RTL synthesis, tightly coupled with floorplanning, which includes placement with global and critical routing
• a silicon-sensitive, RTL-driven analysis tool suite
• an RTL virtual prototype, possibly including visualization technology, to support rapid prototyping and early feedback from the customer

The design entry environment will include behavioral HDL entry, behavioral synthesis, or other various graphical entry techniques used by many electronic system design automation (ESDA), also called electronic system-level (ESL), tools. A complementary language--a system-level design language (SLDL)--that would describe heterogeneous system constraints and design goals is now in its formative stages. The early RTL verification suite will include event-driven and cycle-based simulation, formal verification (equivalence checking and model checking), and emulation, as well as various test bench productivity tools. The heart of this new methodology is the RTL analysis suite, which includes support for timing, power, reliability, and signal integrity analysis. The suite is absolutely critical to the RTL virtual prototype. Although it requires EDA vendors to invest substantially in R&D, it will greatly increase overall design capability and productivity. Finally, the RTL virtual prototype environment can present a more integrated and easy-to-use interface for interacting with the system being designed--a simple set of graphical input controls, a sample video display with spectral analysis, or a full system mock-up.

Yet how can we overcome the accuracy problems that generally plague RTL tools today? The key lies within our current EDA flows. In the sequential paradigm, we essentially complete logical design before beginning physical design. With the advent of more robust floorplanning tools (which are slowly replacing traditional tools that perform placement and global routing), we are seeing a gradual transition toward concurrent logical and physical design. This concurrency means that both logical and physical concerns will be addressed through a process of iterative refinement, so that even at the RT level, many key physical constraints and decisions can be leveraged to improve logical design decisions. A concurrent design architecture is therefore imperative to solving the enormous challenges associated with the integration needs of the RTL-driven analysis suite, synthesis, and floorplanning.

Another factor is that accuracy requirements aren't constant throughout the flow. During the early RTL stages, only relative accuracy is required to help guide the user along one of several alternative paths. During the RTL virtual prototype stage, however, absolute accuracy, because of the likelihood of coming up against real physical limits, takes on a sudden significance. Preference among design choices is not the same thing as acceptability for manufacturing.

The RTL virtual prototype

Just what is an RTL virtual prototype? It's a design methodology that uses a wide range of tools focused on design realization and verification preceding the gate level. Just as EDA tools helped to raise the level of design abstraction from gate-level design to RTL design, we must now complete the transition with tools that allow thorough verification and analysis to occur at the RT level. With the assistance of more complete floorplanning capabilities, such analysis tools can guide design choices earlier in the design cycle, even at the architectural level. Far more than functional simulation, the RTL virtual prototype is a means to study all critical aspects of the design--including timing, power, and even human interfaces--prior to manufacturing.

The philosophy of the RTL virtual prototype is based on several important concepts: concurrent consideration of physical constraints during the functional design stages, a strong shifting of design analysis and verification up to the RT level, and early integration of heterogeneous functionality (which includes both hardware and software, with a user interface prototype). The primary reason for using this methodology is to take advantage of the system-on-a-chip capabilities that are now upon us as we delve into sub-0.25-µm process technologies.

Although the RTL virtual prototype may include a graphical mock-up of the system or advanced visualization of output data (or both), it is not necessarily required. The phrase "virtual prototype" is conceptual--it is not an actual interface. The emphasis should be on the designer's ability to gain a level of confidence in the design that approaches the level he would normally gain through using a physical prototype, which is most often realized through a broad suite of analysis tools, augmented with special hardware-software coverification features.

What tools play a central role?

Tools that take center stage in the new environment include static and/or hybrid timing analysis, power estimation and analysis, floorplanning, and various reliability and signal integrity analyses. As the concurrent EDA flow evolves and matures, the RTL virtual prototype will address electromigration, electrostatic discharge, voltage drop, crosstalk, and even substrate noise. But for the moment, let's focus on timing and power.

Commercial timing analysis products are becoming more tightly integrated with floorplanning, and we'll see this trend continue as we incorporate early physical layout considerations back into the RTL virtual prototype. Today, floorplanning tools use the Standard Delay Format (SDF) to pass timing data back to timing tools, a procedure that is usually sufficient for iterating on smaller portions of a design. Furthermore, inconsistencies can result from using different timing calculation engines in different tools, but can be cumbersome for large designs. Over time, expect both issues to be resolved as more tools embrace Delay Calculation Language compiled timing engines with the DCL procedural interface. Although the designer may be focused on working at the RT level, static timing tools operate at the gate or transistor level, using netlist input with libraries and interconnect delays. Thus the key to a fast prototype is synthesis that can generate gates much faster than full RTL synthesis (preferably behind the scenes). Speeding synthesis becomes a common theme for many analysis tools.

In power analysis, rapid synthesis to a gate level is very useful but not sufficient. Senté's Watt Watcher, for example, performs a behind-the-scenes fast synthesis to incorporate critical library information. In contrast to timing analysis, however, power analysis tools such as Watt Watcher must also use heuristics that statistically improve the end results, because power consumption depends on more variables than gate library and netlist information alone can provide. It is a function of numerous complex variables, such as transistor switching and leakage activity, capacitive loading due to interconnect, dynamic input stimulus over time, and operating frequency. Full analysis would thus require a fully routed transistor-level design, simulating all expected inputs over time. For early estimation purposes, however, we must rely on faster techniques that scale better with design size. One technique that greatly improves accuracy is to collect switching activity from functional simulation and use it to augment the probabilistic (static) analysis mode. Synopsys 's Power Compiler collects this information into its SAIF file format, whereas Senté uses existing HDL PLIs.

The main problem with using a lightweight synthesis process to generate fast gate representations is that the structure and content of the synthesized gate-level netlist isn't necessarily very close to what a full, optimized synthesis tool will produce for the real design implementation. The reason is that full synthesis contains a much richer set of choices and decision graphs for converting RTL intent into optimized gates, as well as substantially different library elements and characteristics for a specific foundry process. The bottom line is that power estimates can never achieve an accuracy of within 15 percent of Spice without adding heuristics based on "lessons learned" experience.

EDA standards play a critical role in supporting the new RTL methodology in three distinct areas: (1) user-tool interfaces, (2) tool-tool interfaces, and (3) library-tool interfaces. The interface with the user is best exemplified by the use of VHDL or Verilog to capture design intent, although in practice we actually deal with subsets of those languages and with specific semantics for synthesis. Any other user input language, whether it be synthesis constraints or a new SLDL, also qualifies.

The critical role of standards

The majority of current EDA standards attempt to facilitate a "plug and play" tool-tool interface between an ever increasing variety of tools that, taken together, make up a useful EDA flow for designers. To date, most have been ASCII file formats. In the future, however, more tool-tool interfaces won't be able to sacrifice this much performance, so industry trends are pointing to in-memory procedural interfaces between tools and databases. Also, because tools are often worthless without the necessary libraries that provide the technology-specific knowledge base, library interfaces too should be interoperable.

The EDA Industry Council Project Technical Advisory Board (PTAB), along with VHDL International and Open Verilog International, have been defining a set of RTL interoperability standards to support the RTL methodology. One component, the RTL language subsets for VHDL and Verilog, is nearly ready for industry adoption. These subsets define not only syntax, but more importantly the semantics for how to describe hardware for consistent synthesis and verification. Another component is the ALF (Advanced Library Format) library, which recently merged with DCL and its successor, DPC (Delay and Power Calculation). A third component is known as RTL constraints, which, once available, will complement the RTL subsets.

The SLDL is a forward-looking, worldwide initiative aimed at addressing system design complexity even before hardware implementation begins with any HDL. SLDL doesn't yet exist; however, initial language requirements specify support for requirement-level constraints that span both hardware and software and permit abstractions over time, communication, and computational models (for more information, see www.si2.org/sld).

Perhaps the greatest imperative of all for EDA standards is to allow concurrent logical and physical design through an open tool flow architecture--exemplified by the Chip Hierarchical Design System (CHDS) technical data standards (CHDStd). CHDS, whose funding from Sematech companies concludes this year, is the only open architecture supporting deep-submicron design needs. As discussed earlier, the RTL virtual prototype requires greater concurrency, and only CHDS provides that concurrency in an environment allowing users to integrate tools from multiple vendors as required for their large and diverse flow requirements. (To learn more about CHDS, see "CHDS: Next Paradigm for Deep-Submicron EDA?" December 1996, p. 42.)

Call to action

Most industry observers agree that our existing design methodologies haven't caught up with manufacturing process technology, and we're long overdue for a major change. The very health of our electronics industry could be at stake--electronics designers and EDA vendors alike are affected. Increasing design complexity alone calls for change, and the need for a new methodology is compounded by the silicon verification challenges so prevalent in this era of deep-submicron geometries.

So the race is on. EDA suppliers are now under pressure to deliver tools that support the new RTL analysis methodology that users need, and users have the responsibility to work with the suppliers to create tools that support their evolving design flows. The unique blend of existing and new EDA technology offers the potential to rise to new levels of design productivity.

To voice an opinion on this or any Integrated System Design article, please email your message to miker@isdmag.com.

integrated system design  April 1998