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Test: The Final Hurdle for Systems on a Chip Embedded ATE addresses concerns about scalability, convergence, and core access, paving the way to faster and more efficient system-on-a-chip testing. by Bernd Koenemann

The advent of million-gate ICs is driving great changes in the EDA environment, from gate- or register-centric to functional, block-based design. This article on embedded ATE is the fourth of a five-part series on issues and trends for the next generation of designs. The previous articles covered the RTL virtual prototype (April) , the requirements for next-generation design languages (July) , and IP and cores from the perspective of the Virtual Socket Interface Alliance and the Silicon Integration Initiative's ASIC Council (August) . The final article will discuss physical verification.

Test is the last hurdle on the path to a successful system-on-a-chip (SOC) project. Runners know that the last hurdle can be particularly difficult to cross, sometimes requiring substantial mental and physical adjustments to help them to the finish line. Likewise, designers, manufacturers, and users of SOC devices must adjust the way they think about and implement test. The SOC industry needs new approaches to implement the testing of hierarchical core-based designs, the functional diversity of the system-level building blocks, and the scaling of several critical parameters of the underlying semiconductor and packaging technologies. Embedding test equipment functions into core-based SOC devices emerges as the most viable practical solution that can address the needs of testing at the chip level.

Figure 1	Core access
Multiplexed access paths allow testing of the embedded cores.

A key driver for SOC design is the promise of packing more functionality onto a single chip in less time than ever before. Design teams can address the squeeze most effectively by extensive reuse of existing embedded cores. However, reuse of cores and the increasing use of RTL design entry conspire to remove designers further from the realities of manufacturing test, making it more difficult to design testable structures and generate the necessary test patterns. Meanwhile, customers are demanding unprecedented levels of product reliability, forcing designers to become more deeply involved in meeting the test challenge. A promising approach to solving the SOC test problem is to extend the notion of "system" to include the tester itself.

Embedded cores

Test is one of the most pressing challenges for SOC because the traditional methodologies and tools aren't appropriate for design processes that rely on the hierarchical reuse of cores. Yet increased integration density requires a commensurate increase in design productivity to maintain time-to-market and time-to-profit rates for new microelectronic products, often necessitating the reuse of cores. To complicate matters, cores come in many different flavors, ranging from soft cores delivered as synthesizable RTL code all the way to hard cores that are already laid out, implemented, and delivered as geometric shapes.

The challenge of integrating multiple cores of various levels of firmness, or implementation detail, into a single SOC has raised enough concerns to motivate the formation of industry associations to set standards. The IEEE P1500 working group is developing architecture and language standards for test interfaces between cores and the surrounding logic. The standards are expected to be ready for voting next June (contact Yervant Zorian at zorian@logicvision.com). The VSIA (Virtual Socket Interface Alliance) Manufacturing Test Development Working Group is developing guidelines for core providers as well as users. They expect to publish their work by the end of the year (contact Rudy Garcia at garciar@sanjose.ate.slb.com or Prab Varma at prab@duettech.com). The key issues these groups are addressing are how cores can be properly prepared and packaged for reuse and what methodologies and tools will be available for chip integration.

Commercial design-for-test and automatic test pattern generation methodologies and tools are completely logic-centric and are suited only to a flat implementation style. The insertion of DFT structures (internal and boundary scan, for example) and test pattern generation are performed on a completely flattened gate-level logic model of the ASIC. Furthermore, test programs assume the use of external testers that have relatively easy access to the flattened design.

When cores enter the picture, the process changes significantly, becoming more hierarchical in nature. How test becomes part of the core package delivered to the SOC integrator depends on the type of core, the DFT structures included, and the amount of detailed information concerning the core internals the core provider is ready to furnish. For example, if the core is a soft block delivered as RTL code or a full gate-level model with scan, then the core model could be merged with other cores and user-defined logic, creating a complete chip representation that's compatible with the traditional DFT and ATPG tools. However, common practice--particularly for high-value hard cores--encapsulates test requirements not in a full gate-level model but rather in a black-box representation with an attached set of predefined test vectors or even a tester-specific test program that must be applied to the I/Os of the core. Clearly, the traditional DFT and ATPG tools aren't designed for this scenario. To apply predefined test vectors or test programs to an embedded core requires that the core I/Os be made accessible from the chip I/Os. The most straightforward method for implementing such access is to insert some form of multiplexing structures around each core (see Figure 1).

Figure 2	The information gap
The bandwidth gap between how much information can be produced and consumed inside a chip (number of transistors per chip times internal clock frequency) and the rate at which information can be transported across the chip I/O interface (number of I/Os times I/O switching frequency) continues to grow rapidly.

Traditionally, designers have had to manually insert necessary access structures for embedded macros (such as memories) into their chip designs, sometimes guided by application notes from the semiconductor providers. In addition, all core-level I/O references in core tests still require translation into chip-level I/O references. The increasing size and complexity of SOCs have only exacerbated the difficulties. It is thus hardly surprising that recently announced DFT tools that automate this process have received considerable attention as offering a major step toward realizing the potential of SOCs.

Convergence and scaling

The core-based design methodology and associated core access problem represent only a small part of the overall SOC test challenge, however. The other major obstacles--technology convergence and scaling--add considerable value to SOC technology, but at the expense of simplicity.

A very fundamental and new characteristic of SOCs not addressed by simple access and test translation methodologies is the convergence of traditionally separate function types on a single chip. At the system level, ASICs are complemented by standard ICs such as stand-alone processors, stand-alone memories, and mixed-signal ICs for interfacing. The traditional partitioning of systems by function type into glue-logic ASICs or function-specific standard ICs has resulted in highly specialized design and test technology directions. The ATE industry, for example, has for many years offered dedicated memory, logic, and mixed-signal testers to match the output of equally dedicated memory, logic, and mixed-signal semiconductor manufacturing lines.

Using different types of testers for different types of functions isn't a problem as long as the different function types are on different chips. In deep and very deep submicron technology, however, chip-level integration density has reached a critical threshold where it suddenly becomes advantageous to integrate all key elements of a typical system--processor, memory, glue logic, and mixed-signal functions--onto a single chip. Embedded memory has the same test requirements as stand-alone memory--highly algorithmic, looped at-speed test programs--and may drive specialized diagnostic requirements to generate repair instructions for large memory cores with built-in redundancy. Though memory testers competently fulfill those requirements, they can't successfully play the role of an ASIC logic tester. Unrolling memory test algorithm loops into stored stimulus and response patterns for a logic tester can very quickly exceed the available pattern buffer. In contrast, specialized memory testers contain algorithmic pattern generation hardware optimized for the highly looped memory test algorithms. But memory testers are normally ill-equipped to deal with the deep stored-pattern buffer requirements for holding the essentially nonalgorithmic logic ATPG stimulus and response patterns.

Trying to solve the SOC testing problem simply by reapplying existing macrotests through some direct access mechanism from the chip I/Os fully exposes the unique test characteristics of each individual macrofunction type to the test equipment. To avoid the need for three or more different testers for each SOC, a new type of ATE that combines logic, memory, and mixed-signal testing features must be created.

Figure 3	Embedded ATE
Embedded ATE blocks generate and analyze function-specific at-speed test vectors and responses inside the system on a chip itself. The externally visible control and result interfaces of the embedded ATE blocks can be fully serviced by very basic and commonly available low-speed low-pin-count logic test equipment.

Understanding the impact of progress on the scale of technological parameters is equally important for planning a viable strategy for SOC testing. Moore's law predicts how the achievable transistor count per chip grows over time; the Semiconductor Industry Association's National Technology Roadmap for Semiconductors lays out the consequences of that prediction. Combining the roadmap numbers for transistor count, chip I/O count, cost, and chip-internal and I/O switching speeds reveals that the rate of growth for how much information can be generated and consumed inside a chip (internal bandwidth, defined as number of transistors per chip times internal switching frequency) outpaces by far the rate at which the available I/O bandwidth grows (number of I/Os times I/O switching speed)(see Figure 2). At the same time, the cost of package pins declines much more slowly than the cost of a transistor. None of this is surprising because the physical characteristics (such as spacing) of external I/Os must remain at a macroscopic level dictated by chip attachment and board manufacturing constraints, whereas the internal feature sizes can rapidly move down from a micro-scale to a nano-scale. In other words, the chip I/Os and board-level interfaces don't scale physically at nearly the rate of the internal circuits, contributing to a growing number of transistors behind each chip I/O and a widening performance gap between the chip internals and the I/O interface.

The amount of test data needed for testing to a certain degree of completeness grows with the transistor count of the function under test. For scan-based logic ATPG vectors, the growth rate is roughly proportional to the growth in transistor count. External test equipment must propagate all stimulus and response data through the chip I/Os, so the pin buffer depth and number of tester cycles required to apply the test grow with the number of transistors per I/O. Since ATE has a fixed bandwidth until it is upgraded to a newer, faster version, growth in integration density constantly threatens to erode the test floor throughput capacity.

No package constraints

SOC internal function partitioning and performance aren't constrained by the cost and performance limitations of chip packaging. This advantage gives SOC designers an opportunity to completely rethink the system partitioning approach, but it also increases the demands on testing. Moving the memory into graphics chips, for example, makes it possible to increase the internal memory data bus to 256 or even 512 bits, with some indication of 1,024-bit buses in the near future, and still fit the overall chip into a relatively low-pin-count package. In other words, the data width of internal macros can easily exceed the number of chip-level I/Os. The test access must then be serialized or the core must be tested in multiple passes that access a subset of outputs on each pass.

The disparity between internal and external switching speeds also challenges test accuracy. Microprocessor speeds, for example, are accelerating at a much greater rate than motherboard speeds. The specifications for internal macrofunctions scale with the internal clock frequency to exploit the higher internal data width and switching speed capabilities, without concern for the stagnant external interface limitations. At the same time, the external I/O interface timing and tolerances must satisfy only the board-level requirements and don't necessarily need to match the internal speed and tolerances. In other words, there can be a significant disparity between the internal at-speed test requirements for an embedded macro in an SOC and the speed and tolerance reasonably offered by I/Os available for external access to the chip. The disparity can make it virtually impossible to deliver an accurate at-speed test to an embedded macro, even if the external ATE and prober/handler interface are fast and accurate enough by themselves.

Embedded ATE to the rescue

Designers can overcome many of these problems by embedding critical ATE functions into the SOC itself. The concept is not new. Embedded memory macros, for example, have been in use for some time, and the industry has already had a taste of how difficult it is to use the existing tool and equipment base to test deeply embedded macros cost-effectively. It's increasingly popular to attack the embedded memory test problem by integrating memory BIST circuits into the SOC. These embedded ATE circuits combine very compact on-chip memory test algorithm generation hardware with a small on-chip controller and on-chip timing generation hardware into what is essentially an on-chip implementation of the algorithm and timing portion of a dedicated memory tester. Embedded ATE can perform high-speed, high-bandwidth, and high-data-volume algorithmic address and data generation, memory access control signal timing, and response comparison directly on the chip without having to navigate the chip I/O bottleneck. As a result, BIST eliminates the need to upgrade logic ATE for memory testing or to use separate memory and logic testers.

Figure 4	The cost of ATE
The average cost contribution of traditional ATE to the overall manufacturing cost of a chip is between 3 and 5 percent. At 400,000 to 500,00 gates, the relative silicon cost of embedded ATE (up to 10,000 equivalent gates) matches that of external ATE. For systems on a chip of more than 1 million gates, the relative silicon cost of an embedded ATE implementation falls below 1 percent.

Embeddable ATE blocks are now commercially available for at-speed testing of scan-based logic and embedded SRAM, DRAM, ROM, and other memory types, as well as of some mixed-signal blocks (such as PLLs and converters) most commonly used in large, mostly digital SOCs. All embedded ATE blocks should have a low-bandwidth, purely digital control and result interface for communication with very basic existing or new external digital ATE. All internal at-speed timing signals are derived on-chip from a single precise clock input. This reference clock (in most cases a system clock for the SOC) is the only high-speed signal needed from an external source. The normal power supplies are the only analog reference signals needed for the embedded mixed-signal ATE.

For additional utility, all external control and result communication with embedded ATE blocks should be integrated through an industry-standard IEEE 1149.1 test access port. This optional configuration makes much of the power of high-performance ATE functions accessible to the user through widely available IEEE 1149.1 equipment and test or diagnostic software environments. The approach removes thorough testing of complex SOCs from its exclusive venue of semiconductor manufacturing test floors with their highly specialized and expensive ATE, making such testing equally available in the lab, for burn-in, and at the board and system level, as well as in the field (see Figure 3).

Implementing testing functions on-chip means that the embedded ATE naturally scales with the underlying semiconductor technology. On the other hand, the viability of external test methods continues to erode under the rapid growth of integration density, because ATE access is constrained by the bottleneck of an external chip I/O interface that scales at a much lower rate. Embedded ATE, in contrast, actually benefits from technology progress by taking full advantage of the gains in chip-internal density, bandwidth, and performance.

The cost of embedded ATE

The technical problems of external testing and the availability of technical solutions for embedded ATE are by themselves not enough to justify the cost of an early transition. An industrywide transition on a large scale typically occurs only when a new method is available, has established technical power, and provides clear economic benefits over an existing method. Embedded ATE meets the first two criteria with ease, and industrywide trends show that economic conditions clearly favor its use in today's dense SOCs.

Semiconductor industry data suggest that the capital investment for semiconductor ATE purchases has remained more or less stable at between 1.5 and 2.5 percent of worldwide semiconductor industry revenues. Assuming that semiconductor manufacturing costs represent about 50 percent of semiconductor revenues, ATE accounts for an average of 3 to 5 percent of all semiconductor manufacturing costs. Test engineering costs plus ATE maintenance and operational costs double or triple the cost of the ATE (yielding the total manufacturing test cost), and since those ratios haven't changed dramatically over the past five years, it's reasonable to assume that they will remain constant, barring fundamental changes.

The manufacturing-related price for embedded ATE is paid in terms of the additional silicon needed to integrate the ATE functions. Using commercial embedded ATE technology, designers can implement the high-speed pattern generation, response processing, and timing signal generation needed for at-speed testing of a state-of-the-art SOC in about 5,000 to 10,000 logic gate equivalents, assuming that a scan infrastructure is already in place. For designs of about 400,000 to 500,000 gates, the relative silicon cost of embedded ATE equals the cost of external ATE, making the SOC generation the crossover point where embedded ATE becomes an indisputably favorable alternative to total reliance on external ATE, and for above a million gates, the investment constitutes less than 1 percent of the manufacturing costs of today's generation of ICs (see Figure 4).

As SOC design techniques intensify in pursuit of smaller, faster, and cheaper end products, the need for more efficient testing methods will only increase. Embedded ATE offers a solution that is scalable in terms of both complexity and performance, that can expect a long life, and that offers savings in time as well as direct equipment costs. Somehow that last hurdle doesn't look so bad after all.

Bernd Koenemann is vice president of products and solutions at Logicvision, Inc. in San Jose. He has been active in the field of test technology and design automation for 20 years and is a pioneer of BIST technology. He holds several U.S. and international patents on BIST and test and has published over 20 technical papers in international journals and conference proceedings.

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integrated system design  October 1998