design flow

Physical Verification: Challenges and Problems for New Designs Next-generation designs will require changes in design methodologies--and substantial changes to the tools themselves. by Tets Maniwa

The advent of million-gate ICs is driving great changes in the EDA environment, from gate- or register-centric to functional, block-based design. This article, on physical verification, is the last of a five-part series on issues and trends for the next generation of designs. The other articles have covered the RTL virtual prototype (April, p. 22), the requirements for next-generation design languages (July, p. 26), IP and cores from the perspective of the Virtual Socket Interface Alliance and Silicon Integration Initiative's ASIC Council (August, p. 52), and test (October, p. 36).

A large part of the EDA industry is looking at the issues of nanometer designs and how to address the growing need for better tools and methodologies. The growing design gap between silicon capabilities and EDA tools is increasing the requirements for faster and more accurate analysis in the nanometer, or very deep submicron, technology generations.

The debate focuses on the need for a new design tool set to address the physical verification problem in today's nanometer designs. One key element of the set will be an RTL floorplanner that can effectively communicate physical design constraints to front-end design tools. A problem confronting the tool set, though, is that of managing the data explosion that accompanies chip designs containing over 5 million transistors. Though the nature of the ultimate solution remains undetermined, the industry appears to agree on at least one point: The current crop of solutions still falls short.

The main problem is that the tools need to work at a very high level to complete a design within the allotted time, but the high-speed signals require that the physical verification of the design be done at greater levels of detail and accuracy, which takes much more time.

Mark Goode, vice president of ASIC development at ASIC International in Knoxville, Tenn., argues that simply extending current tools may not suffice: "The problem is that currently not a single EDA company has all the necessary pieces and the integration of point tools has problems. When one vendor changes versions, many of the hooks into the next tool aren't supported properly. I don't think we need a new tool set. I think we just need a tool set."

The necessary intervention may come in the form of a master tool, a push toward tool suites over point tools, or even a Perl script to automate the interactions among point tools. Of course, the peripatetic history of the industry suggests that the solution may come from an entirely unexpected direction. In any case, the need to use core-based design styles and extensive hierarchy for multimillion-gate designs will require the close integration of front-end and back-end tools to facilitate the smooth flow of design intent and information.

Industry opinion seems divided over the need for brand-new tools to achieve the necessary integration. Gadi Singer, general manager of design technology at Intel Corp. in Santa Clara, Calif., and chairman of the Silicon Integration Initiative's Industry Council in Austin, Texas, believes that "current tools can be extended to perform at 0.18 micron."

Changing channels
Design engineers and their software tools continue to raise the levels of abstraction in their work. The ability to generate ever more gates in the same or less time has increased by orders of magnitude over the past 10 years. The design flows, however, haven't changed nearly as much. Designers continue to throw their netlists over the wall to CAD, where the CAD person converts the netlist into a physical design.

Previous process generations required only DRC, ERC, and LVS for release to tape-out. Now, in designs with nanometer geometries, the timing analysis is just the first of many analyses for the physical verification of the design. The RTL physical verification tool set for the future will need to address--in addition to the basic place-and-route and timing functions--simultaneous solutions to the problems of power, signal integrity, electromagnetic interference, metal migration and reliability, and thermal effects (see the figure).

Accurate assessment of the trade-offs among the critical parameters calls for breaking down the barriers between design, synthesis, physical design, and physical verification. Otherwise, placement solutions resulting from a point tool perspective for one problem may exacerbate other problems. Such a design method is chaotic, because the rubberbanding of lines to make adjustments to correct a problem in one area, such as timing violations, can push other parameters, such as power or signal integrity, out of tolerance.

Greater accuracy in any individual analysis can't come at the expense of the overall design specifications. After all, what's the use of running a tool that dramatically reduces the power requirements of the design, only to have the timing analysis tool unable to verify the design at the specified power? Each type of tool will need to encompass some aspects of the other tools to perform its job properly. At the same time, however, the tools need to address the appropriate levels of data exchange without repeating calculations and data generation (see "Addressing the Speed/Accuracy Trade-off in Parasitic Extraction").

Figure	The new physical verification methodology
The next generation of designs will require more physical analysis at the design level while using the floorplanner as a link between logical and physical design.

One logical step toward convergence is to redesign the design flow itself. "We'd like to see some of those verification steps at the front end of the design cycle," says Vassilios Gerousis, a senior member of the technical staff of Motorola, Inc.'s Semiconductor Products Sector in Phoenix. "To move some of the verification to the front of the design process, we require tool interactivity. The ideal scenario is to get budgeting defined at the start of the design cycle and refine to actual constraints during the design flow, which includes power, timing, signal integrity, metal migration, and reliability. Budgeting, constraints, connectivity, and parasitics are some of the data sharing required for those tools." Clearly, the design flow of the future must run forward and backward.

As one of the key tools for the design flow, the next-generation RTL floorplanner becomes the bridge between the logical and physical design spaces. It acts as the constraint identifier and manager and also becomes the communications medium between the logic design and physical design groups.

Floorplanning and beyond
ASIC International's Goode finds current floorplanners unable to meet their new role. "Floorplanning needs to occur between Boolean conversion of RTL and optimization. That requirement is very difficult to meet, because most floorplanning tools require gates that aren't available until the first pass at optimization is complete. If you try to do a floorplan from RTL and then synthesize, you wind up repeating a good deal of work because the assumptions you made about the way the RTL would synthesize may not be accurate."

For example, an m by n multiply function is described in a single line of code, C = A * B, but can result in hundreds to thousands of gates, depending on the underlying algorithms and architecture. An implementation with many pipeline stages for full floating-point math will use more gates and power than a multiplier that does just a barrel shift and add. The complex multiplier will require significantly more detail and accuracy in the RTL floorplan than does the simple unit, to take full advantage of the extra circuitry without sacrificing the performance in the interconnect.

Richard Tobias, president and COO of White Eagle Systems Technology, Inc. in San Jose, is one of those who zeroes in on the RTL floorplanner and its link to the physical design. "The key to getting the million-gate circuit out the door is the interaction between synthesizer and floorplanner. The next generation of enhanced LVS and checker tools need to link the RTL and the final layout," he stresses.

The enhanced role of the RTL floorplanner has a cascading effect on other tools and on methodologies. As designers start to use RTL floorplanners to address more of the physical effects in their designs, the CAD engineers must find ways to solve all of the local and global issues. Because the problems are independent and interactive, the design community and the tool vendors need to develop new methodologies to identify, locate, and resolve the problems and achieve convergence of all the parameters in the design.

John McGehee, a consultant at Voom in Sunnyvale, Calif., just finished a million-gate ASIC layout. "Now, engineers use place-and-route tools, then apply the verification tools and get back a list of errors and coordinates. Next, they manually go to the coordinate and review the issue, then either ignore the error message or correct the problem," he notes.

McGehee points out that convergence ushers in a new level of complexity: "With thermal and other higher-end analysis results, the question is what to do with the error message. The designer can't just move something and stretch out the wiring like a DRC error. Somehow, a message has to get back to the place-and-route tool to identify the problem and physical area. All of the analyses are interrelated, so a better connection with the extraction, analysis, and place-and-route tools is needed and, in addition, a methodology for fixing the errors."

Greater reliance on automation to solve the problem may be warranted and is probably inevitable. Peter Richmond, manager of strategic and product marketing in the System IC Division of Toshiba America Electronic Components, Inc. in San Jose, says, "One key is to automate the solutions in layout to address the signal integrity and EMI issues. The advent of large bus structures and other heavily loaded nets requires high-power signals--relative to the rest of the logic--to drive the lines. The increase in the masses of signal activity creates additional situations for signal interactions."

George Costakas, director and principal engineer at Puyallup Integrated Circuit Co. (Picco) in Federal Way, Wash., adds a cautionary note. "There are problems with letting the software become more important in decision-making about IC design features. Today's software has too many bugs even for the relatively simple tasks it has to address. I can't imagine letting a more complex design go automatically through a tool and letting the tool make very important decisions without some human intelligence guiding it to fix the problem nets."

Toshiba's Richmond concurs: "Point tools don't always fix the problems. At the netlist level, the user needs to intervene in the process manually. Extraction and analysis are difficult and currently require lots of manual intervention. But the manual intervention depends on hierarchy and overall methodology, which makes the automated solution currently much more difficult and possibly unsolvable."

Data explosion
The conflict between the requirements for greater accuracy and higher throughput means that data reduction or critical element identification will become an integral part of the tool set. The size of the netlists and data sets also will mandate much more highly integrated databases as well as intelligent parsing and reduction mechanisms to permit a variable analysis. The tool set will have to understand the design hierarchy and adjust the level of accuracy to match the working level.

In addition to providing the type and detail of the information needed to describe the problem areas, the tools will have to address the great increase in data volume and types. "Tools have a lot of overhead for storing their data," Picco's Costakas observes. "Designs require thousands of bytes for each gate. The current limit for large workstations is a few gigabytes--much less than the data size for future design sizes." Among the solutions are data reduction or compression, database structures that allow better data sharing among analysis sections, and the use of hierarchical methods to allow the design structure to help with the partitioning tasks.

One way to address the data explosion is to use the design hierarchy to determine the work at the RT level as well as other levels. Hierarchical structures help the designer keep track of the various substructures but don't help the physical design and verification processes. To allow the implementation of hierarchical methods in physical design requires substantial changes in the tools and design flows. The basic issue is the need for obtaining more detail without overloading the computers with excessive data.

Tobias of White Eagle sees the modularity produced by hierarchy as the greatest challenge. "In the future, we'll need to understand how to characterize a section of the chip as a black box, so we won't have to do the IC as a flat full chip but as a collection of blocks. The difficult part of the design is work on the timing and interfaces between the blocks."

Voom's McGehee illustrates another problem: "We need to have the placement portion doing its work in smaller chunks, whereas the global routing needs to have the whole design available to know where it can reroute. The next generation of place-and-route tools needs to address hierarchy in the design, since all of the other tools seem to do their job in smaller chunks at a time. We need to have better tools to complete the task."

The introduction of hierarchy makes data management critical, because the partitioning of the design into smaller units with multiple levels requires careful tracking of all the pieces. For example, a tool needs to ensure that the net names and signals are carried throughout the design without losing or adding any additional instances of a net name. That task won't be easy when the design contains 10 million gates and over 100 million nets. "A 10-million-gate design will generate far more raw data than current operating systems can handle, mandating new approaches to database compression and selection of critical data," says Tobias.

The cutting function is yet another issue raised by hierarchy. If a design is partitioned into levels, where does the level end--at the output of one level, or the input of the next? A designer may break the hierarchy at functional boundaries or synthesizable block levels, but the design may not have logical breaks at the same level. For example, in the logical representation, some of the glue logic lies at the top level, because the gates are necessary to mate the separate blocks. Actually, however, they're connected at some lower peer level in the physical design.

In spite of the difficulties, the use of hierarchy in a physical design and verification flow helps tremendously by breaking the tasks into smaller, more manageable subtasks. As the tool vendors and users gain more experience with the details of implementation and the use of hierarchy in the design flow, the general and specific solutions will emerge. Toshiba's Richmond cites yet one more reason to attend to hierarchy. "Data size and data management is becoming an issue, especially for designs with IP from multiple vendors. The different vendors don't make sure their designs are able to map to the extraction and verification tools," he says.

The design community and the EDA vendors need to look carefully at the issues arising from the ongoing changes in the silicon design space. Nanometer processes will enable ICs to hold tens to hundreds of millions of gates in the next decade, but the capacity may not be available to the users if the tools can't verify the physical design. The challenge for the EDA vendors is to make multivariate analysis available earlier in the design cycle. The users and the EDA companies will also need to develop new methodologies to go with the enhanced tools to make the next-generation designs practical. No matter what solutions surface--master tools, suites, scripts, or something else--the question is not whether, but when.

To voice an opinion on this or any Integrated System Design article, please email your message to miker@isdmag.com.

integrated system design  November 1998