design tools

Who Will Lead the Development of the System-on-a-Chip Industry? Leaders of SI2's ASIC Council and VSIA go head to head in their perspectives on who will develop the standards for IP and the future of the system-on-a-chip industry itself.

The advent of million-gate ICs is driving great changes in the EDA environment, from gate- or register-centric to functional, block-based design. This article, on the areas of intellectual property and standards from the perspective of the ASIC Council and the Virtual Socket Interface Alliance, is the third of a five-part series on issues and trends for the next generation of designs. Part 1 examined the need for a comprehensive RTL methodology (April), and Part 2 discussed the requirements for a new design definition language at the system level. The other articles will cover physical verification and the testing of deeply embedded system-on-a-chip ICs.

Everyone agrees that designs exceeding a million gates will require both design reuse and methods to verify system functions with virtual prototypes. The missing elements are the tools and standards to facilitate block-based design.

Although they have overlapping membership, the ASIC Council of the Silicon Integration Initiative and the Virtual Socket Interface Association have notably different perspectives on the nature of the standards and capabilities needed to implement systems on a chip. Here, senior representatives of each organization present their views on the issues facing the use of intellectual property and try to define the changes necessary to make the system-on-a-chip industry a reality.

SI2's perspective

Improved EDA capabilities, silicon integration know-how, and practical industry collaboration can significantly improve IP reuse over time. We believe that SI2's ASIC Council, driven by customer needs and with clear business interests and a strong body of experience, is well positioned to answer the challenge.

In April 1995, representatives of five of the world's leading semiconductor manufacturers gathered to consider future challenges and factors impeding progress toward single-chip system integration. After they compared viewpoints, it quickly became clear that there was common ground in terms of reducing the engineering costs for complex chip designs, speeding the pace of EDA innovation, and building the infrastructure for the emerging system-on-a-chip market.

To better understand the tasks at hand, the companies funded a lab that tested the compliance of EDA tools (in this case, Verilog simulators) by pooling their leading-edge libraries and test cases toward determining design sign-off criteria. The findings were to form a baseline for tests of more tools, eventually including the whole front-end ASIC flow. The trial, performed under contract to SI2, proved successful in reducing the deltas among Verilog simulators, as well as lowering ASIC tool support costs and evaluation time.

Advisory board
On the customer front, SI2's ASIC Council initiated a customer advisory board (CAB) made up of leading system-on-a-chip consumers such as Ericsson, Hewlett-Packard, Nortel, Silicon Graphics, and Sun Microsystems. The purpose of the group was to provide guidance to the Council's efforts. Beyond approving the initial steps, the CAB suggested two important courses of action. First, make schedules for ASIC design flows more predictable; second, consider the broader implications of the emerging system-on-a-chip capability for the consumer OEM.

To execute the first task, the council benchmarked timing convergence in each member company's flows, thus providing a relevant measure of the propensity for a series of critical paths to move within acceptable limits. This new form of design analysis is currently being used to meter designs between some CAB and ASIC Council members. Additionally, the sheer capacity of the newer silicon processes caused such concern that there is now an initiative to develop benchmarks that will stress the limits of EDA tools, hopefully expediting improvement efforts.

In the second course of action, the council learned from the members' customers that the need for portable IP and design reuse stemmed from the following facts: silicon processes requiring end product redesign are quickly becoming obsolete; incorporation of IP from other sources, reducing sole-source supplier dependency, is widely practiced; and design margins and market windows are becoming scarce. Another underlying issue is an apparent role reversal whereby silicon suppliers become system integrators, which gives end-consumer product IP unprecedented exposure.

After several meetings and long discussions on the outcome of CAB's recommendations, the council reached several conclusions that formed the basis for its current agenda.

Expectations
System-on-a-chip expectations are too high. Typically 25 percent or less of a single-chip system design is synthesizable logic, and many include mixed-signal sections requiring a great deal of nonreusable, design-specific engineering effort. Further, chips with 1 million gates or more cannot be easily populated with IP blocks averaging from 15,000 to 25,000 gates each that would leave the designer to consider the block-level interconnect for 40 to 60 subsystems, in addition to large blocks of embedded memory or large, fixed cores. The popular market message that customers need only to buy commercial EDA tools, a third-party cell library, and IP blocks, then snap them together like Lego blocks for transmittal to a variety of foundries, is oversimplified at best.

Standards are necessary but not sufficient. The formation of VSIA, though welcomed as an initiative with heavy EDA sponsorship, is addressing a only a subset of the issues required to foster system-on-a-chip market growth and design reuse capabilities. Standards evolve over time and are most successfully driven by de facto implementation, so the council's role is complementary in the sense that it is very much a focused acceleration and implementation group. An example of this complementary relationship is its effort to represent technology libraries with the Open Library API (OLA), a combination of the Advanced Library Format (ALF) and Delay and Power Calculation Language (DCL), which are commercially available.

EDA companies lack fundamental capabilities. The ASIC flows in the late '80s and early '90s popularized tools such as HDL simulation and synthesis, which let EDA companies improve aging methodologies incrementally--thus addressing impending process and design reuse requirements. A bifurcation of the present course is occurring, though. On one hand, more abstract input for design content and constraints is needed; on the other hand, companies need more precise models of silicon behavior. Addressing those issues will require risk taking, longer-term planning, verification, and management on the part of leading EDA companies.

Business issues, more than technology, are limiting the mix and match of high-value IP. The market value of third-party IP directly correlates with its reproducibility in silicon according to advertised specifications. The expertise required to extract the specified performance typically lies in the leading semiconductor suppliers, who possess a wealth of oftentimes similar IP. A further complication is that customers of large silicon suppliers with deep pockets increasingly expect the supplier to indemnify them for patent infringement involving their outsourced IP.

Thus convinced that the business end was the bottleneck, the CAB representatives proclaimed that the technical issues would be resolved once the semiconductor and IP suppliers adopted or formed an accepted IP business model.

To address these main concerns, then, the ASIC Council committed to the following goals in order to improve customer relations:

1. Accelerate development of a system-on-a-chip infrastructure. This goal entails setting a practical baseline from which to enable IP portability and reuse--internally and with customers. The first objective is to develop a common technology library representation that will facilitate design portability across commercial EDA tools (hence OLA). Currently, libraries must be customized for each EDA tool and silicon process, presenting a major obstacle to reuse. The selection and prototype of the common representation is currently under way.

2. Improve EDA to meet silicon capabilities. Silicon suppliers implement a variety of methods to improve their process and manufacturing technology, but the design and EDA sector lack such measures. The council is planning development of EDA benchmarks in order to determine overall performance and design capacity for 0.18-µm processes and beyond.

3. Address the business issues. The council is studying business model and legal issues in hopes of improving responsiveness to customer requests to include or exchange IP with third parties. Answering the simple question of whom to call when the silicon doesn't work is a major issue. Longer term, other industries' practices may influence open IP commerce, such as the way record companies pay royalties to multiple artists and assume sole responsibility for distributing their work.

Joined by NEC in early 1997, with more members still to come, the ASIC Council companies have combined annual revenues of more than $156 billion and a commanding share of the system-on-a-chip market--according to Dataquest's system-level integration market survey. The members are leading companies with the broadest IP portfolios, highest levels of system-on-a-chip experience, and unmatched customer and application focus.

As EDA companies strive to offer a range of system-on-a-chip services and IP provision continues to be a burgeoning cottage industry, it all comes down to who can deliver the necessary performance and functionality. Customers want leading single-chip technology and supplier confidence in equal measures.

For more information on SI2 and the ASIC Council, visit www.si2.org.

Andrew Graham is the president of Silicon Integration Intiative, Inc. in Austin, Texas.

VSIA's perspective

The integration of reusable IP in chip designs has been a staple of engineering for some time. Recently, shrinking design cycles and device densities that accommodate entire systems have prompted designers to increase their reliance on reusable IP. One industry analyst estimates that the total value of virtual components (VCs) available in-house or through the market will more than double to $25 billion by the end of 2000. This growth illustrates a clear trend toward core-based designs that will accelerate as the system-on-a-chip industry gains in sophistication and reach.

The most important issue facing designers will be the creation of an effective standard interface between the myriad virtual components needed to create systems on a chip. Dataquest notes that the system-on-a-chip market itself will grow from today's $4 billion to $19 billion by 2001. Without such a plug-and-play interface, this growth will be unrealized as designers spend too much time and money getting the pieces to work.

Fortunately, forward-looking system, semiconductor, EDA, and IP companies recognized this need and joined together to identify the standards needed to address the important challenges faced by the system-on-a-chip industry. The resulting organization, VSIA, now comprises more than 180 members, including representatives from all segments of the system-on-a-chip industry. Its goal is to accelerate the growth of the system-on-a-chip market by identifying the open technical standards that enable the exchange of VCs on an intra- and inter-company basis. Currently, seven development working groups are working on a wide range of design issues.

Rapid progress
VSIA's vision has taken hold. The number of new IP companies is growing and many established companies are adapting their business models to enter this fast-moving and lucrative market. System integrators are investing in design flow changes to accelerate the pace of development. In anticipation of the release of VSIA specifications, EDA vendors are adjusting tools and flows.

Fueling the growth of IP companies is the rapid proliferation of new specifications. For example, specifications from the Implementation/Verification Development Working Group (DWG) and the Analog/Mixed Signal DWG specifying the data formats for hard VC blocks have cleared the exhaustive member review process and were released to the public.

In addition, the Attributes Specification from the On-Chip Bus DWG has been written and is undergoing membership review. This standard interface specification will help those designers who are not bus experts understand the terminology and technical attributes of bus structures in order to compare and evaluate buses. It's the key to permitting compatibility of VCs in multiple bus environments.

All the DWGs have made significant progress. The IP Protection DWG has determined that a variety of techniques are required to protect VCs and that a decision tree approach is better than reliance on encryption. The System-Level Design DWG is finalizing its taxonomy and terminology guidelines. The Manufacturing-Related Test DWG is specifying the format for describing the test vectors to be passed between VC providers and the integrator, as well as between the integrator and test engineering.

The next step
The crafting of specifications to enable compatibility of VCs is at the heart of VSIA, and the DWGs have made significant progress toward creating a comprehensive set. Certainly, more needs to be done, and the creation of specifications will continue. But with some specs ready for public dissemination, it also is time to begin the adoption process.

Adoption of specifications is a major undertaking for both VSIA and the industry. EDA companies will need to modify parts of their products to read or generate new or modified data formats. In some cases, the modifications will affect tools and design flows. VC developers will have to change their cores to align with bus and test standards. System integrators will need to optimize design flows around these new modifications. To accommodate VC standards, test equipment suppliers may need to alter software or hardware.

In the end, the benefits of these changes will far outweigh the investment required. Fewer data formats will be required, a single VC will be usable by a broader range of customers, and integrators will be able to simplify or automate much of the design flows.

For VSIA to see widespread adoption of its standards will require demonstration and validation of its work. VSIA pilot projects--exercises, tests or validations of new specifications or methodologies--are an opportunity for companies to implement the new system-on-a-chip design reuse methods and for the DWGs to verify them.

In general, pilot projects benefit both VSIA and the pilot participants with the knowledge gained during the test and can serve as a trial run before using fully developed processes. The implications of the pilot effort for a specification will be shared with member companies, enabling those who validated the specification to have a direct impact on VSIA standards.

Looking forward
Now that the flow of specifications has started, it's reasonable for those who have worked so hard to develop them to ask when the standards will begin to show benefits. VSIA forecasts that the first specifications will be included in fully released tools and design flows late this year or early 1999. Of course, VSIA members who have been actively engaged in DWG development--as well as those who have aligned their internal design efforts with the direction of the DWGs--will enjoy as much as a year's lead in understanding and adopting the specifications.

The momentum toward interface standards for VCs is building with the rapid development of specifications. As interest builds and membership grows, new challenges will be identified and met. The key to this is to maintain a broad-based membership. That's why VSIA welcomes participation from industries ranging from system integrators, to EDA, to VC developers, to silicon manufacturers, to even the foundries serving the fabless business model.

For more information, please visit www.vsi.org.

Douglas Fairbairn is the president of the San Jose­based Virtual Socket Interface Alliance and vice president of embedded software services at Cadence Design Systems, Inc., also in San Jose.

Diana Anderson heads the VSIA's committee for pilot programs and is the director for corporate strategy at Cadence Design Systems.

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integrated system design  August 1998