Design for Test

The problem of testing complex system-on-a-chip designs is complicated when they contain cores from third-party vendors. As circuits of system-level proportions are etched in silicon, such critical signal paths as address and data buses become inaccessible to conventional test and debugging tools like logic analyzers, in-circuit emulators, and microprocessor development systems. Consequently, design and test methods must change to meet the challenge of system-level integration on deep-submicron (DSM) circuits.

We tested a 400,000-gate circuit, called Los Gatos, that contains large reusable cores. These include a 32-bit embedded PicoJava processor; several RAM and ROM modules; a PCI interface; and peripherals for controlling audio, graphics, and display functions testing (see Figure 1). To test the chip, we used a combination of three different test strategies--built-in self-test (BIST) to attack the memories, automatic test pattern generation (ATPG) programs, and partial scan for on-chip testing, as well as boundary scan for easier production testing (see Figure 2). During the process, we found that design techniques can help minimize the cost of those strategies.

The Los Gatos chip is built using a 0.35-µm, 3.3-V CMOS process. It operates at a maximum clock rate of 66 MHz and comes in a 240-pin PQFP. Los Gatos is intended as a low-cost, single-chip foundation for networked consumer applications like television Web browsers, network computers, and Internet appliances.

Built with soft cores, it uses a design hierarchy that simplifies logic synthesis and design verification. The top level contains all of the main modules, including the central processor; UART; and graphics, CRT, and memory controllers. The clock generation and reset generation modules, as well as the test access port (TAP), boundary scan register, and pad ring, are also placed at the top level

The chip has four independent clocks: 66 MHz for the processor; 32.768 MHz for the real-time clock; 33 MHz for the PCI interface; and 50, 12.625, and 15.75 MHz for the network computer, NTSC, and PAL video formats, respectively. The design and test methodology takes into account multiple clocks, which in turn affect logic synthesis and automatic test pattern generation.

Test imperative Because the chip was fabricated with standard cells using Passport libraries from Compass Design Automation (now part of Avanti), it was insufficiently characterized for process engineers to understand the possible memory failure mechanisms. Its new embedded processor, memory compilers, and memory cell designs compounded the problem. Therefore it was essential for the chip's designers to be able to check for process errors and to fully verify the new PicoJava architecture.

Our goal was to achieve 95 percent fault coverage. The purpose of such high fault coverage was to ensure a low defect rate, which is expected and necessary for high-volume, consumer applications. The designers, however, knew that it was impractical and too expensive for their team to generate and use the millions of patterns necessary to verify the chip's functions.

We decided to combine the separate tests for individual cores into one approach that would test the entire chip. Part of the challenge was that some of the chip's cores are latch-based--an approach that reduces the core size but precludes testing using automatic test pattern generation. In addition, nearly one third of the chip consists of embedded RAM and ROM, making it critical that we find all memory faults.

To test a chip as large and as complex as Los Gatos, such conventional silicon and board test and troubleshooting techniques as wafer probing and in-circuit emulation are inadequate. The chip was therefore designed to include BIST and TAP structures that enable both chip- and board-level testing. Specifically, the test methodology involves BIST for embedded memories, internal scan for on-chip logic, and boundary scan for debugging the silicon as well as testing and debugging board-level products such as an evaluation board.

To make BIST possible, stimulus generators and response analyzers were embedded on the chip, obviating the need to develop and verify test vectors and store them in costly automated testers. Moreover, BIST allows at-speed testing, which is necessary for revealing high-speed failure mechanisms in DSM circuits.

Design for test To minimize chip area overhead, the designers used a top-down approach for adding the required BIST circuitry so that it could be shared by several memories where possible. (In contrast, a bottom-up approach presumes that the memory models will have BIST circuits in place when the memory is compiled. The advantage of this approach is that the BIST circuits are added automatically; the disadvantage is that a high area overhead is incurred if the chip includes several small memories.)

Figure 1. Designed as the foundation for Internet appliances and related consumer products, the 400,000-gate Los Gatos includes a PicoJava embedded processor, several RAM and ROM blocks, a PCI core, and peripheral control logic.

In the top-down approach, a memory compiler creates the behavioral models for all the embedded memories and adds them to the design to create a full simulation model. The designer then identifies those memories that, based on their similar size and hierarchy, can efficiently share the BIST circuitry. This approach reduces the BIST circuit overhead. These memories are grouped into modules, and the BIST circuits are then added. Finally, all of the BIST circuits are connected to the global TAP that controls them. To generate the BIST circuits, the designers used Genesys Testware's Memory BISTcore.

Figure 2. To test the Los Gatos chip and diagnose faults, designers added internal-scan, BIST, and boundary scan circuits. The design and test methodology takes into account multiple clocks, which in turn affect logic synthesis and automatic test pattern generation.

A logical decision For testing the logic section, the daunting task of writing and running millions of functional test vectors forced us to adopt a near-full-scan design methodology. This methodology allowed us to use proven ATPG tools that automatically generate high-fault-coverage manufacturing test patterns. Although some third-party cores in the design were latch-based and couldn't be converted for scan testing, ATPG software generated a set of tests that detects over 90 percent of single stuck-at faults in the logic.

Multiplexed D flip-flops from the circuit library were inserted to serve as the scan circuits. Applied in this way and given the chip's seven different clock domains, the flip-flops are susceptible to race conditions when shifting data out. The race conditions arise because the delay among different clock trees can't be guaranteed during the physical design. To solve this problem, we created separate scan chains--one for each internal clock domain. Therefore the clocks--those generated internally as well as the clocks for the chip's several ripple carry counters--had to be bypassed, because they couldn't be synchronized for scan testing.

To simplify the insertion of scan devices, the designers opted for a hierarchical design. Consistent with the design's core-based methodology, scan devices were first inserted into each core. The engineers designed, verified, synthesized, and inserted the scan chains for each of the chip's major modules. In cores that had multiple clocks, separate scan chains were created for each clock. Design rules for each core were checked to detect potential scan chain problems. Then the designers connected the scan chains at the top level of the design and rechecked them to ensure chip-wide integrity. Only then were test patterns generated on the final gate-level netlist.

Controlling the clocks All of Los Gatos's test and debugging features are controlled by an advanced TAP, which serves as a standard interface to the BIST controllers and scan chains. Although the TAP complies with the IEEE 1149.1 boundary scan standard, it also includes several "private" instructions--neither mandatory nor optional as defined by the standard--that help solve the problem of assembling internal scan chains in different clock domains. For example, the TAP's clock control register meets the requirement to bypass the chip's internally generated clocks. Also, the TAP can insert "lockup flip-flops" between scan chains, which prevent race conditions between flip-flops in different clock domains by switching on the clock's trailing edge rather than its leading edge.

The TAP also can control each internal clock. In this way, it prevents timing problems when patterns created by the ATPG tool are captured. Races occur during the capture of scan patterns whose sources and target flip-flops exist in different clock domains. The TAP's clock control register, coupled with special ATPG test protocols, allows only one internal clock to pulse during a capture operation. During shift operations, however, the TAP lets all internal clocks pulse.

The TAP's scan dump facility lets an engineer stop a functional test at any point and shift out the contents of the on-chip registers to find failed gates or modules. Also, by loading internal scan chains with the original register contents, the engineer can continue the functional test from where he left off.

At the board level, the TAP can help pinpoint subtle errors in the interplay between hardware and firmware--a tough task when the processor and memory exist on a single chip. For example, the TAP's control of the embedded processor's debug and breakpoint registers lets an external tester monitor details of the processor status that aren't otherwise available at the package pins. In addition, the TAP's clock control register can stop the processor clocks while letting clocks to the peripheral cores continue.

Boundary scan on-board The designers used boundary scan to test the application evaluation board for Los Gatos. The two main components were the boundary scan register and the TAP that controls it. In addition, a boundary scan cell is associated with each I/O pad. To add the boundary scan components, designers relied on Boundary Scancore, a Genesys Testware tool that allows for multiple BIST controllers and scan chains.

Gate fee Test elements require a lot of die area that the designer could use for other functions or compress to reduce the chip's size. In the case of Los Gatos, the internal-scan, memory BIST, boundary scan, and TAP circuits require about 38,500 gates (see Table 1). Of those, about 22,600 accrue from the internal scan registers.

Of the remaining gates, RAM module BIST circuits consume some 5,500 gates, and the ROM BIST circuitry occupies almost 3,800 gates. The designer could reduce both of those figures by using partial sharing of BIST circuits (the actual design as described includes only complete sharing).

The designer could also reduce the gate count by compressing the ROM contents in both space and time to obtain the cyclic-redundancy-check signature for testing. The boundary scan circuits occupy about 6,600 gates--1,900 for the TAP and 4,700 for the boundary scan chain. This portion of the gate count can be lowered by simplifying the TAP's clock control register and by using simpler boundary scan cells at the input pins.

Other test capabilities The scan logic and boundary scan components pave a practical path for running chip- and board-level manufacturing tests. They also aid in verifying and debugging the first prototypes of system-on-a-chip products, for which troubleshooting can be brutal. As with the chip, conventional in-circuit emulation and logic analysis techniques are of little use for boards when the CPU address and data pins are inaccessible. The TAP becomes a pivotal debugging aide when used with functional tests. *

Ki Joo Jeong is a group leader in the Java Products Group of LG Semicon Co., Ltd. (Seoul, South Korea).

Srini Krishnaswami is the engineering manager at Advancel Logic Corp. (San Jose).

Bejoy G. Oomman is the president of Genesys Testware (Fremont, Calif.).

Shankar G. Hemmady is the president of Guru Technologies, Inc. (Cupertino, Calif.).

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integrated system design  February 1998