TOOLS AND TECHNOLOGIES Products and services for system design

Physical simulation Raphael NES 2.0, a 3D physical simulation package capable of accurately extracting capacitance directly from complex VLSI layouts, offers a new tiling feature that improves storage and CPU time and lets the user extract critical capacitance values from GDS II input files with more than 250,000 nets. The tool consists of several modules: gds2cap 2.1.1 and Quickcap 2.1 from Random Logic Corp. and TMA Layout 1.5 and the Raphael-to-Quickcap converter. The numerical engine, Quickcap, uses a Monte Carlo technique to solve 3D capacitance directly from the Laplace equation. It can handle complex VLSI wiring with conformal dielectrics and nonplanarized structures. The simulator is available now for Unix-based workstations from Digital Equipment, Hewlett-Packard, IBM, and Sun Microsystems. Pricing starts at $81,250. Technology Modeling Associates, Inc., Sunnyvale, Calif. Contact (408) 328-0930 or www.tmai.com.

Design planner Logic Design Planner-DSM combines Cadence's back-end IC design technology with a front-end design planning tool. The front-end floorplanner has been enhanced to include the Qplace placement system, as well as global routing techniques from the WARP router. Logic Design Planner-DSM drives timing-driven Qplace with chip-level boundary constraints, such as input edge rate, drive resistance, and output load, in addition to SDF path constraints, providing convergence of full-chip and critical-path timing. The tool provides final Qplace placement results to the back-end routing environment. Timing predictability throughout the deep-submicron flow is achieved by using identical delay calculation algorithms and timing models. Logic Design Planner-DSM uses the Timing Library Format (TLF) 3.0, shared by Cadence's front-end and back-end tools, and its delay calculation technology has been correlated to the entire deep-submicron flow. The tool is available now for $98,000 (fully configured) and is being shipped in volume. Cadence Design Systems, Inc., San Jose, Calif. Contact (408) 746-6223 or www.cadence.com.

FPGA design Destination FPGA Series 2.0, a complete, vendor-specific FPGA design environment for mixed schematic and HDL design, is available for $4,995 for Windows 95 or Windows NT machines. The environment incorporates design process management, schematic entry, context sensitive VHDL editor, a graphic stimulus generator, VHDL simulation, Synopsys FPGA Express-based synthesis, and a fully integrated design kit to support Altera, Lucent ORCA, or Xilinx devices. Actel and other vendors, as well as a Verilog version, will be added in early 1998. Options include graphical high-level design for $1,800 and an interactive HDL tutorial for $500. The series can be upgraded to the Veribest FPGA Desktop, a fully integrated, vendor-independent FPGA design solution using Synopsys 's FPGA Express synthesizer. Six months of product support and a 30-day money-back offer are included. Veribest, Inc., Boulder, Colo. Contact (800) Veribest or www.veribest.com.

CPLD The latest member of the Max 9000A family, the EPM9560A product-term-based CPLD, offers pin-to-pin performance of 10 ns and price savings of up to 60 percent over Max 9000 devices. Manufactured with a 0.5-µm, triple-layer-metal CMOS process, it has 560 macrocells and is pin-, function-, and programming file-compatible with the Max 9000 family. The device operates at 5.0 V and contains Altera's Multivolt feature, which allows it to interface with devices operating at 3.3 V. It also offers in-system programmability, which enables engineers to program it using automated test equipment, embedded processors, or the Altera Byteblaster parallel port download cable that connects directly to the PCB. The device is fully supported by Altera's Max+Plus II development software and is available now in a variety of packaging options at $29.75 apiece in high volumes. Altera Corp., San Jose, Calif. Contact (800) 9-ALTERA or www.newscom.com.

System design With Systemview by Elanix v2.0, designers can simulate and test communications, digital signal processing, and RF/analog systems. Highlights include a boost in simulation engine performance, enhanced model libraries, and an optional simulation accelerator called Automatic Program Generation (APG). A completely automated tool that speeds Systemview models, APG works by automatically generating a Windows EXE or DLL from a Systemview block diagram; after compilation, the 32-bit EXE will run faster than the original in the Systemview design environment. Results from an APG execution are viewed within the Systemview analysis environment and exported for analysis in any standard spreadsheet or data visualization software. Available now for Windows NT and Windows 95 platforms, Systemview starts at $3,495, and the APG option costs $2,495. Elanix, Inc. Westlake Village, Calif. Contact (818) 597-1414 or www.elanix.com.

Memory generators The Process-Perfect LP133 family of single- and dual-port SRAM generators is designed specifically for systems requiring extremely low power consumption with good performance and high density. Power consumption is 0.2 mW/MHz at 1.8 V for 64-kbit single-port SRAMs and 0.4 mW/MHz for 64-kbit dual-port SRAMs. Both can operate at speeds of 133 MHz. The LP133 uses Process-Perfect techniques to fine-tune each delivery for the customer's semiconductor process. Tuning includes circuit redesigns (when necessary), transistor size tuning, layout tuning for the process, and extraction and characterization using the customer's electrical models. The LP133-SS single-port synchronous SRAM generator and LP133-DS dual-port synchronous SRAM generator are available now. Pricing for semiconductor manufacturers starts at $475,000 per generator, which includes all Process-Perfect circuit and layout optimizations, characterization, and modeling, as well as the ability to distribute the generators to both internal and external users. Artisan Components, Inc., Sunnyvale, Calif. Contact (408) 734-5600 or www.artisan.com.

Analysis tool Ampredictor 3.0 Signal Integrity Analyzer (SIA) features an enhanced net topology editor, which offers direct linkage to the Ampredictor circuit simulator, and the AmpSpice circuit simulator, an enhanced version of Berkeley 3F5. AmpSpice offers a "virtual scope" format with enhanced functionality for measuring rise and fall times, delays, overshoot and undershoot, and for evaluating cross-talk effects, setting noise margins, and performing timing analyses. The analyzer also includes a 2D field solver that generates lossy transmission line models of PCBs and a model library manager containing an extensive collection of single- and multi-line connector models. New mathematical functions include multiplication, division, integration, and fast Fourier transform for frequency domain analysis. Direct access to the Amp electronic catalog, Amp Connect, is provided. The analyzer is scheduled for general availability at the end of February and is currently priced at $8,500 for a single-user license. Amp, Inc., Harrisburg, Pa. Contact (800) 522-6752 or www.connect.amp.com.

IBIS model development Targeted at IBIS (I/O Buffer Information Specification) model developers, the IBIS Model Development System includes a specialized visual editor for creating, maintaining, and checking the syntax of IBIS models; a transmission line simulator that allows testing of models under a variety of real-world loading conditions and reads IBIS models natively; additional utilities to speed the creation of models; and application notes on the IBIS standard and how to create models with it. The development system is available now. It runs on Windows 95 and Windows NT. There is no cost for semiconductor companies developing IBIS models for public consumption. Hyperlinx, Redmond, Wash. Contact (425) 869-2320 or www.hyperlynx.com.

Core suite A suite of cores that supports the Spartan series of FPGAs is available from both Xilinx and its Alliancecore partners. Included in the suite are UARTs, microprocessor peripherals, Reed-Solomon and Viterbi codecs, RISC processors, and Xilinx's DSP Logicore products. In addition, the Logicore PCI interface is expected to be available the end of March. Xilinx, Inc., San Jose, Calif. Contact (408) 559-7778 or www.xilinx.com.

RTL testability tool An RTL testability analyzer, Turbocheck-RTL checks Verilog RTL designs before synthesis and verification. The tool can identify most test rule violations, such as combinational feedback loops, generated clocks, gated clocks, asynchronous set/reset, and floating buses. A beta version is shipping now. Production versions ship in March and cost $20,000. Syntest Technologies, Inc., Sunnyvale, Calif. Contact (408) 720-9956 or www.syntest.com.

PCB design The Interconnectix tool suite unites signal integrity and timing analysis with floorplanning and placement and routing. Using the suite, engineers can create electrically correct, manufacturable designs in one pass to meet their time-to-market goals. Enhancements include a complete what-if analysis environment that allows for signal integrity, timing, and layout exploration in a "sandbox" environment before a design schematic is available. The package supports user-definable corner-case analysis, allowing engineers to evaluate best- and worst-case timing and signal integrity parameters throughout the design process. It's available immediately and includes Tau for board-level timing analysis, at $35,000; the IS_Floorplanner for hierarchical floorplanning and analysis, at $58,000; the IS_Multiboard at $15,000; the IS_Optimizer at $35,000; and the IS_Synthesizer at $75,000. Platforms supported include HP-UX, SunOS and Solaris, and AIX. Mentor Graphics Corp., Wilsonville, Ore. Contact (800) 685-7000 or www.mentorg.com.

Virtual prototyping Version 3.0 of the EDAnavigator virtual prototyping software for design planning and analysis of PCBs and multiboard systems uses two new tools--Net Explorer and System Engineer--to enable engineers to define constraints and make trade-offs between signal integrity and other issues earlier in the design process than previous releases. Net Explorer is an environment for net topology definition and signal integrity analysis before a schematic is completed. It incorporates a layer stackup editor and EDAnavigator's electronic constraint manager. System Engineer provides floorplanning, partitioning, and trade-off analysis capabilities during the rest of the design process. It creates an environment for placement review, preroute analysis, and final postroute analysis and verification. EDAnavigator supports a variety of CAE and CAD design environments, including mixed-vendor environments. Net Explorer starts at $10,000, and System Engineer at $26,500; and one System Engineer license supports multiple Net Explorer licenses. Both tools are available now for Windows and Unix systems. Xynetix Design Systems, Inc., Fishers, N.Y. Contact (800) 334-0663 or www.xynetix.com.

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integrated system design  March 1998