TOOLS AND TECHNOLOGIES Products and services for IC and electronic system design

Analysis tool Powerexpress NT, a design and analysis package for power converters, integrates Analogy's Saberdesigner NT technology for design creation and graphical waveform analysis with the Saber mixed-signal simulator. The tool includes the new Powerexpress Template Library, which incorporates over 300 simulation models for power electronic designs and features many of Analogy's capabilities for power converter design. The library offers a physics-based model for IGBTs and a series of advances in non-linear magnetics modeling, as well as models for power MOSFETs, power diodes, PWM circuits, and other vital power converter components. Powerexpress NT is available now for Windows NT platforms. The package also includes Saberscope, Sabersketch, and Inspecs Stress. The initial version is priced at $19,950, which includes technical support by e-mail. Analogy, Inc., Beaverton, Ore. Contact (503) 626-9700 or www.analogy.com.

Verification tool A formal verification tool for equivalency checking of million-gate, system-on-a-chip (SOC) designs, Formality is tightly integrated with Synopsys Design Compiler and complements Primetime, Synopsys 's static timing analyzer. Using Formality and Primetime together in a synthesis-based design flow, designers can exhaustively verify the functionality and timing of a design. Formality can read Design Compiler synthesis libraries and can also import Verilog simulation libraries. It contains multiple solvers for proving equivalence. As it analyzes a design, it automatically applies the solvers that are best suited to each design structure encountered. The tool also automatically manages hierarchy, allowing users to verify designs when the hierarchy doesn't match. All debugging information is presented in the context of the original design source, thereby providing diagnoses in a form most familiar to the designer. The tool is well suited to design projects in which a high percentage of the logic is synthesized with Design Compiler, each IC is larger than 100,000 gates (or the equivalent), and gate-level simulation is expected to run for several days. It is available now for $100,000. Synopsys , Inc. Mountain View, Calif. Contact (800) 388-9125 or www. Synopsys .com.

C-to-Verilog C2Verilog compiles C designs and algorithms into RTL Verilog that can be synthesized into FPGA and ASIC hardware. It supports the complete ANSI C language without requiring special commands or C restrictions. It performs code optimization to create RTL Verilog that synthesizes more efficiently in hardware compared with previous attempts using line-by-line syntax translation. The designer can specify directives to the compiler using a set of options selected from the command line or GUI. The generated RTL Verilog code is compatible with synthesizers from Synopsys , Exemplar, and Synplicity, as well as Verilog simulators from Cadence, Model Technologies, and others. The tool runs on SunOS, Solaris, HP-UX, and Windows 95 and NT systems and is available now for $9,500 (node-locked license). Compilogic Corp., San Jose, Calif. (408) 369-0555 or www.compilogic.com.

Modeling and analysis The latest release of Alta Bones Designer enables system-level designers of communications, networking, and multimedia products to characterize the functionality of complex systems, reuse existing subsystem components in model development, and share critical design information between system and chip verification environments. New features include dynamic modeling capabilities, a TCP/IP library that speeds system construction, support for Open Model Interface­compliant models, import of system models developed using the Specification and Description Language (SDL), and a simulation interface tool kit for interfacing the tool with other commercial and proprietary applications. The software allows systems designers to dynamically vary the structure of the model throughout the system-level simulation. It also provides high-level performance analysis of networks incorporating TCP/IP and allows detailed studies of the interaction between TCP and other protocols. The TCP/IP library suite includes the TCP, UDP, IP, ICMP, and ARP protocols. It is available now, with prices starting at $36,000 for Unix-based workstations from Sun and Hewlett-Packard. Cadence Design Systems, Inc. San Jose, Calif. Contact (408) 943-1234 or www.cadence.com.

Networking cores Five new cores targeted at asynchronous-transfer-mode (ATM) networking applications are the first ATM-specific cores from Xilinx's Alliancecore program, and have been optimized for the XC4000 FPGAs and the new Spartan series. The functions consist of a 50-MHz Utopia slave interface, cell delineation and cell assembler circuits, and CRC10 and CRC32 error detection and correction cores. Thus they provide some of the fundamental ATM building blocks for developing flexible network interface controller, segmentation and reassembly, and transmission convergence circuits. The Utopia slave is priced at $18,000, the cell delineation and cell assembler circuits are jointly priced at $12,000, and CRC10 and CRC32 cores are jointly priced at $7,000. VHDL source code with synthesis scripts is available for an additional cost. Coreel Microsystems, Inc. San Jose, Calif. Contact (510) 770-2277 or www.coreel.com.

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integrated system design  April 1998