TOOLS AND TECHNOLOGIES Products and services for IC and electronic system design

DSP design environment Xilinx DSP is a fully integrated DSP design environment that consists of the XC4000X and Spartan series of FPGAs; a wide range of DSP cores; the Core Generator software integrated with system-level modeling and simulation tools, such as Systemview from Elanix, Inc. (Westlake Village, Calif.); and prototyping systems, such as the GVA-200 DSP hardware accelerator from GV and Associates, Inc. (Ramona, Calif.). Xilinx DSP currently supports more than 20 DSP Logicore modules, including filters, correlators, transforms, integrators, sine/cosine building blocks, math functions, and memories. DSP Logicore functions can be used with standard hardware design environments. A prototyping platform, the GVA­200 DSP hardware accelerator, is available from GV and Associates; it's used to prototype DSP algorithms in Xilinx FPGAs, including the Spartan series. The Core Generator tool and DSP Logicore functions are available now at no charge. Systemview by Elanix with the Xilinx DSP support is available now from Elanix starting at $2,495. The GVA-200 DSP Hardware Accelerator system starts at $1,950 in single-unit quantities. Xilinx, Inc., San Jose, Calif. Contact (408) 559-7778 or www.xilinx. com.

Logic synthesizer Synplify 5.0 offers a multilevel timing constraints management system. Its new synthesis constraints optimization environment (SCOPE) provides a single graphical entry and editing environment for five different categories of constraints, including "-improve," which is designed to force critical path optimization during synthesis, and "-route," which enables users to factor actual place-and-route delays into the design optimization process. Synplify 5.0 is available and is priced the same as previous versions: $12,000 for node-locked licenses for Windows and $24,000 for floating licenses for Windows and Unix. Current Synplify customers on maintenance will be upgraded at no additional cost. Synplicity, Inc., Sunnyvale, Calif. Contact (408) 617-6000 or www.synplicity.com.

Model checker Version 2.0 of the Formalcheck model checker includes a command-line interface for both queries and commands, automates the creation of families of queries with similar properties, and supports interface standards. It is priced at $150,000 for a floating license and includes both Verilog and VHDL front ends, a GUI with source code viewer and command line text interface, basic query templates, the complete set of formal verification algorithms, and a waveform viewer with back references to source code. It runs on the Solaris and HP-UX platforms and is available now. Bell Labs Design Automation, Murray Hill, N.J. Contact (800) 875-6590 or www.bell-labs.com/org/blda.

PCI tool Based on HP's PCI verification tool for 32-bit digital designs, the HP E2926A test card is a 64-bit PCI exerciser and analyzer that can test both 64- and 32-bit designs. It features traffic generation capabilities, a real-time PCI protocol observer, and an on-board PCI state logic analyzer. The card can be fully integrated into the user's test software and programmed using the C API. It costs $10,900 and will be available in July. Hewlett-Packard Company, Palo Alto, Calif. Contact www.hp.com/go/tmdir.

Plastic-packaged FPGAs Plastic-packaged versions of the PASIC 1 and PASIC 3 families of FPGAs have been qualified and tested to operate over the military temperature range. PASIC 3 components feature standby current consumption as low as 500 µA, resulting in standby power consumption of 1.65 mW. The QL24x32B from the PASIC 1 family is available now and shipping in production quantities. The first plastic PASIC 3 device, the QL3025, begins shipping in June. Pricing for the PASIC 3 family of military-temperature plastic devices starts at $97.50 in 10,000-piece quantities. Quicklogic Corp., Sunnyvale, Calif. Contact (408) 990-4000 or www.quicklogic.com.

PLD for PCI The EPF10K30A is aimed at 66-MHz PCI systems. Delivering up to 126-MHz system speeds for an 8-bit, 16-tap FIR filter, it has 30,000 gates, 12 kbits of embedded RAM, and Altera's Multivolt I/O interface. It also includes I/O clamping diodes, which are required for electrical compliance with the 3.3-V PCI specification. Optimized for a 0.35-mm, four-layer-metal SRAM process, the device contains 1,728 logic elements and is supported by the Max+Plus II development system for PC and workstation platforms. It is available now in a 208-pin PQFP and will soon be available in 144-pin TQFP, 240-pin PQFP, 356-pin standard BGA, and 256-pin and 484-pin fine-line BGA packages. By year's end, volume pricing is projected to be $15 in 25,000-unit quantities. Altera Corp., San Jose. Contact (800) 9-ALTERA or www.altera.com.

Cell-based library The SYM10 cell-based library contains a wide range of cell drive strengths, for such applications as personal computers, workstations, drive electronics, and communication systems. Manufactured in a 2.5-V, 0.25-µm (drawn) CMOS process with three to six metal layers, the library also supports 5-V-tolerant and 5-V-drive I/O, as well as conventional 2.5- and 3.3-V I/O. Dual-oxide processing allows 3.3- and 5-V I/O, single-ended SCSI, and universal PCI. The library is compatible with existing Symbios cores, including networking, DSP, RISC, SCSI, PCI, USB, and high-speed serial I/O functions, such as 1394 and Fibre Channel. Analog functions, including 10-bit A/D and D/A converters, a bandgap voltage reference accurate to within 1.5 percent, op amps, comparators, and switches, are available. In addition, a frequency synthesizer supports clock generation up to 600 MHz, and PLL-based data recovery circuits provide serial interfaces at up to 2-GHz data rates. The library is available now. Volume production of designs can be expected in early 1999. Design kits are available through the Symbios OEM sales channel and will be backward-compatible with previous libraries. Symbios Inc., Fort Collins, Colo. Contact (800) 856-3093 or www.symbios. com.

NT verification tool Calibre DRC for Windows NT enables system-on-a-chip verification teams to perform design rule checking across Unix and PC platforms. Calibre models the effects of hierarchical design reuse and is methodology-independent. It's available now. Current Calibre DRC and DRC-H customers will receive an upgrade free of charge. Pricing remains the same for both versions, starting at $50,000. The software can be downloaded from Mentor Graphics' Web site at www.mentorg.com/dsm. Mentor Graphics Corp., Wilsonville, Ore. Contact (800) 685-7000 or www.mentorg.com.

ATE testing ICBIST3.0, an embedded ATE tool for at-speed testing and diagnosis of digital and mixed-signal system-on-a-chip devices, offers a scalable and reusable test strategy and will be in production in July. Pricing is based on a per-IC-design NRE model starting at $30,000. Packages vary depending on the specific test and diagnostic options selected. Logicvision, Inc., San Jose, Calif. Contact (408) 453-0146 or www.logicvision.com.

Java language tools Microtec's Java tool kit includes a Microtec Java compiler, the Xray debugger, and a Java run-time system. Xray debugger fully supports Java's object-oriented language constructs and multithreading, with options such as a PowerPC instruction-set simulator, a PowerPC background debugging mode connection, and the Hewlett-Packard PowerPC processor probe. The tools are compatible with existing C and C++ code and will support C and C++ function calls from Java. Beta versions for Windows 95, Windows NT, and Solaris hosts are available for the PowerPC architecture. Pricing starts at $2,300 for a single-user license. Microtec, San Jose, Calif. Contact (800) 950-5554 or www.mentorg.com/microtec.

Fast-turn arrays The 0.35-µm CX3000 series of gate arrays support up to 1.5 million logic gates and up to 416 kbits of embedded memory. Using a three- or four-layer metal interconnect structure, the gate arrays feature a density of 12,000 to 13,000 gates/mm ² and power consumption of 0.1 µW/MHz/gate. They offer 3.3-V, 5-V, or mixed-voltage I/Os, and 5-V I/O tolerance, with a 3.3-V core. The series consists of two families: the CX3001, for prototyping and low-volume production; and the CX3002, for high-volume production. The density for the families ranges from 14,000 to 1.5 million logic gates plus 8 to 416 kbits of embedded configurable SRAM or ROM, with 100 to 608 I/O pads. A variety of other I/O features are available, including 3.3-V PCI compliance at 66 MHz, and USB support. In addition, all family members include up to four embedded analog phase-locked loops and support full-scan ATPG. A wide range of packaging types is available, including PQFP, up to 240 pins; PGA, up to 391 pins; and BGA, up to 553 pins. Full production volume is expected to start early in the third quarter. A CX3001 family member with 500,000 logic gates plus 416 kbits of memory in a typical package is priced at $127 each for a 3,000-device order, and the lead time is 4 weeks. A CX3002 device with 350,000 logic gates plus 96 kbits of memory is priced at $15 each for 100,000 units, and the lead time is 8 to 12 weeks. Chip Express Corp., Santa Clara, Calif. Contact (408) 988-2445 or www.chipexpress.com.

Microcontroller starter kit The AT89/90 series flash microcontroller starter kit is an evaluation tool that can be used as a development environment for Atmel's 8-bit flash AVR microcontrollers. It has an evaluation board that supports all AT90S AVR microcontrollers, including external peripherals and AVR Studio, and can be purchased for $49 from any Atmel distributor or directly from Atmel's Web site. AVR Studio is also available separately and free of charge from the site. Atmel Corp., San Jose, Calif. Contact (800) 292-8635 or www.atmel.com.

Schematic design OrCAD Capture 7.2 adds several new capabilities, including orthogonal rubberbanding and a new autowire feature that automatically creates wires between connected parts. It also includes interfaces for common PCB packages, such as those from Cadence, PADS, and Zuken-Redac. A new API supports creation of customized netlists and reports with Microsoft Visual Basic. The release is now shipping worldwide. It costs $1,295 and an annual extended support option costs $295. Customers with a Capture product that's covered by a new product warranty or an OrCAD extended support option will receive the 7.2 upgrade at no charge. OrCAD, Inc., Beaverton, Ore. Contact (800) 671-9505 or www.orcad.com.

PCI bus core The 64-bit PCI bus target megafunction runs at 33 MHz in compliance with PCI Local Bus Specification Rev. 2.1 and supports burst transfers up to 266 Mbytes/s. A fully customizable core, it features zero-wait-state data transfers and compile times of under 10 minutes on either the Flex 10K or 6000K families. It's available now for evaluation through Altera's Opencore program at no charge through PLD Application's Web site at www.plda.com. Pricing for an encrypted netlist begins at $9,500 and includes a symbol file, timing assignments, a simulation file, and an installation guide. Altera Corp., San Jose, Calif. Contact (800) 9-ALTERA or www.altera.com.

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integrated system design  June 1998