TOOLS AND TECHNOLOGIES Products and services for IC and electronic system design

Layout conversion environment LACE 4.0. converts hard intellectual property (IP) for use in deep-submicron system-on-a-chip applications. The tool uses an interprocess control algorithm to distribute a design over a local-area network and to run a multilevel hierarchy design conversion in parallel. It offers predefined conversion and optimization templates that cover the majority of conversion tasks and includes LACEedit, a layout polygon editor. LACE 4.0 will be available in September for Unix and Linux users on Sun, HP, and Pentium-based machines. Several licensing options are available. Pricing begins at $50,000. Rubicad Corp., San Jose, Calif. Contact (408) 995-3334 or www.edac.org/Rubicad.

Microcontroller in-circuit emulator The MegaICE real-time in-circuit emulator offers real-time emulation for Atmel's megaAVR microcontrollers. The emulator supports flash memory densities of up to 128 kbytes, plus 4 kbytes of EEPROM and SRAM densities as high as 64 kbytes. Providing access to all of the megaAVR's I/O pins, the device emulates any megaAVR peripheral set, including full-duplex UARTs; timer/counters; real-time clock; and megaAVR's 10-bit, 8-channel A/D converter. It uses AVR Studio architectural simulator for its front end. The product runs under Windows 95 and Windows NT and is available now from any Atmel distributor. It's priced at $3,495 each. AVR Studio is included with MegaICE and is available as freeware from Atmel's Web site. Atmel Corp., San Jose, Calif. Contact (800) 292-8635 or www.atmel.com.

CPLDs The Ultra37000 CPLD family consists of seven devices ranging from 32 to 512 macrocells. They're available in both 3.3-V and 5-V versions, and the 3.3-V devices are 5-V tolerant. They're supported by Cypress's Warp design tools. The family consists of the 32-macrocell Ultra-37032, the 64-macrocell Ultra37064, the 128-macrocell Ultra37128, the 192-macrocell Ultra37192, the 256-macrocell Ultra37256, the 384-macrocell Ultra-37384, and the 512-macrocell Ultra37512. Samples of the 7.5-ns Ultra- 37256 are available now. Pricing will range from $1.25 for the Ultra37032 to $49.00 for the Ultra37512, both in high-volume quantities. Cypress Semiconductor Corp., San Jose, Calif. Contact (800) 858-1810 or www.cypress.com.

Reliability circuit simulators BTABERT-EM, BTABERT-TDDB, and BTABERT-HCI are deep-submicron reliability circuit simulators. BTABERT-EM predicts electromigration reliability, BTABERT-TDDB predicts oxide wear-out reliability, and BTABERT-HCI predicts hot-carrier­induced degradation. The simulator modules are available now for BTA's BTABERT reliability simulator and work with either Cadence's Spectre or Avanti's Hspice simulators. BTABERT-EM uses both AC and DC models to predict failure in digital CMOS circuits; BTABERT-TDDB simulates oxide breakdown; and BTABERT-HCI characterizes hot-carrier library cells, builds delay models, extracts switching activities, and predicts clock skew change. The BTABERT reliability simulator with EM, TDDB, and HCI modules is $64,000 and is available now. Each module is available separately with the BTABERT simulator for $40,000. Volume discounts and site licenses are also available. BTA Technology, Inc., Santa Clara, Calif. Contact (408) 986-1011 or www.btat.com.

Simulation environment Simulation Desktop is a visual environment for creating and managing simulation projects. It allows designers to integrate schematics, model sources, and simulators through a graphical user interface and generates structural Verilog netlists and test fixtures based on user preferences. Its relational database provides enterprise-wide library management and reporting capabilities. It facilitates incremental simulation by synchronizing output files with changes made to the design. Simulation Desktop supports the Synopsys Smartmodel library of behavioral simulation models and Verilog models from sources ranging from FPGA vendors to individual designers. It includes support for netlist formats for schematic packages, such as EDIF and any OVI-compliant Verilog simulator. The software is available now, and a floating license on Windows NT starts at $5,000. Simerica Logic Semantics, San Carlos, Calif. Contact (650) 592-6705 or www.simerica.com.

IP protection IP Guard is an intellectual property (IP) protection system. It creates protected models using a proprietary compilation technology that optimizes and reduces the model. The process begins with input source processing and construction of a language-independent representation. The code generation system takes the generic representation and user directives to create a model targeted for VHDL and Verilog simulators. The protection scheme includes irreversible operations. It leverages VHDL, Verilog, ANSI C, SDF, and VITAL, and it generates protected models from a variety of input formats, including VHDL, Verilog, C, and graphics from Designbook. It comes bundled with three copies of Designbook and 40 hours of consulting time. It runs on Microsoft Windows, Sun, and Hewlett-Packard platforms. Pricing starts at $224,000. Escalade Corp., Santa Clara, Calif. Contact (408) 654-1600 or www.escalade.com.

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integrated system design  July 1998