TOOLS AND TECHNOLOGIES Products and services for IC and electronic system design

0.18-µm memory generators The HS500 family of single- and dual-port synchronous SRAM generators produce memories for 0.18-µm process technologies that can operate at system speeds in excess of 500 MHz worst case and 850 MHz typical. The generators are supported by Verilog and VHDL simulation models, Cadence TLF and Synopsys Design Compiler timing models, Motive models, LEF for Silicon Ensemble and compatibles, GDS-II, and others. They feature Universal Test Interface (UTI) support, which is included in all generated memories, and are available now. Artisan Components, Inc., Sunnyvale, Calif. Contact (408) 734-5600 or www.artisan.com.

Mixed-signal BIST Based on Opmaxx's oscillation BIST technology, BISTmaxx provides a uniform approach for testing analog, mixed-signal, and digital circuits. The first in a family of tools, it enables IP providers to incorporate test methodologies into their cores, supporting at-speed testing at all stages of production. The tool also facilitates remote in-field testing for telecommunications and military systems. It is available immediately, with licensing starting at $25,000. Engineering consulting services also are available. Opmaxx, Inc., Beaverton, Ore. Contact (503) 520-9200 or www.opmaxx.com.

Timing analyzer Mach TA accelerates and verifies transistor-level timing of deep-submicron digital and mixed-signal IC designs. A dynamic timing analyzer, it provides interactive verification and accepts a standard Spice netlist in either Star-Hspice format or Eldo format. The netlist can be created by any schematic capture or parasitic extraction tool. The results from Mach TA are displayed with a waveform viewer or as text. It costs $75,000 for node-locked licenses and $93,750 for floating licenses. It is available on HP and Sun Unix platforms immediately and on Windows NT platforms in Q3. Mentor Graphics Corp., Wilsonville, Ore. Contact (503) 685-7000 or www.mentorg.com.

Extraction tool The OptEM Inspector extracts devices, nets, interpolation-based 2.5D interconnect capacitances, and interconnect resistances and performs frequency-dependent RC model reduction. A basic extractor, it sells for $19,900. The substrate resistance extraction (BEM-based 3D and interpolation methods) and the BEM-based 3D capacitance extraction options are available as add-ons for $5,000 each. The "bundled" version of OptEM Inspector, which includes the basic extraction and both the 3D capacitance and substrate resistance extraction options, costs $26,910. The tool is available now on HP and Sun workstations. OptEM Engineering, Inc., Calgary, Alta. Contact (403) 289-0499 or www.optem.com.

IP modeler Visual IP creates and distributes protected IP models and related documentation. Primarily for independent IP creators and silicon vendors, it includes an IP model compiler to create protected visual IP (VIP) models and an IP model manager that reads and simulates the models. The IP model compiler allows IP creators to develop a single-source model of their core in either VHDL or Verilog. The product then compiles the core and related design, verification, and documentation data into a protected model. It is available immediately; pricing starts at $100,000 for a node-locked license, and site licenses are available. Initial simulators supported are Model Technology's Modelsim, Cadence's Leapfrog and Verilog-XL, and Synopsys 's VCS and VSS. The product runs on Sun, HP, and IBM workstations and on Windows 95 and NT PCs. Summit Design, Inc., Beaverton, Ore. Contact (503) 643-9281 or www.summit-design.com.

Programmable logic The ispGDX120A programmable logic device features any-input-to-any-output signal delays of 5 ns, clock-to-output delays of 5 ns, and a maximum operating frequency of 111 MHz. It includes 120 special-purpose programmable I/O cells interconnected by a global routing pool, a 4:1 high-speed input multiplexer, registered outputs, three-state or open-drain output options, IEEE 1149.1 logic, ispJTAGTM in-system programming, and PCI-compatible outputs. The ispGDX120A comes in 160-pin PQFP and a 176-pin TQFP. It is supported by the ispGDX Development System software, available to customers free of charge from Lattice's Web site from the command line. In 1,000-piece quantities, the 5-ns ispGDX120A-5 is priced at $15.95 and the 7-ns ispGDX120A-7 at $10.80 in the PQFP. In 176-TQFP, the prices are $17.50 and $12.35. Both packages are available now. Lattice Semiconductor Corp., Hillsboro, Ore. Contact (503) 681-0118 or www.latticesemi.com.

Model protection IP Guard is coupled with Designbook to create protected models used in system-on-a-chip design. It creates protected models using a proprietary compilation technology that optimizes, reduces, and accelerates the model. The protection process begins with input source processing through Designbook and construction of a language-independent representation that is optimized to create a reduced model. The code generation system takes the generic representation along with user directives to create a model targeted for VHDL and Verilog HDL simulators. The protection scheme includes irreversible operations and is not subject to decryption attacks. A flexible collation process permits the aggregation of multiple modules into a single protected model. IP Guard is compatible with VHDL, Verilog, C, SDF; it accepts a variety of input formats, including VHDL, Verilog, C, and graphics from Designbook. The combination enables viewing of IP vendor-specified internal registers, instruction tracing, checkpointing, expanded error messages, and timing back annotation. IP Guard comes bundled with three copies of Designbook and 40 hours of consulting time. It runs on Sun and HP workstations and Windows PCs. Pricing starts at $228,000. Escalade Corp., Santa Clara, Calif. Contact (408) 654-1605 or www.escalade.com.

Design reuse environment The IP Gear family of tools implements and supports design reuse environments. IP Gear addresses management challenges of efficiency, accessibility, and security with reuse tools that are targeted at essential elements, such as vaults for IP storage, support, and access. The new tools are tightly integrated with Synchronicity's Web-based project and design management environments. Pricing starts at $100,000. Synchronicity, Inc., Marlboro, Mass. Contact (508) 485-4122 or www.syncinc.com.

Code coverage HDLscore combines the Vericov line coverage tool with State-score, a tool for automatic extraction and coverage of finite state machines. HDLscore provides automatic FSM extraction technology so that coverage of finite state machines and their transitions can be analyzed without user intervention. It measures the quality of simulation tests that have been applied to a design. The product works with behavioral, structural, and gate-level code and supports up to six different types of user-selectable coverage. Line coverage types are block, path, and expression; state machine coverage types include states, transitions, and state sequences. HDLscore is available immediately for Verilog simulators that support standard PLIs. A single-seat floating license is priced at $22,000. Vericov and State-score single-seat licenses can be upgraded to HDLscore licenses for $7,000. Initial platforms include SunOS, Solaris, and HP-UX. Summit Design, Inc., Beaverton, Ore. Contact (503) 643-9281 or www.summit-design.com.

Verification tools The Quickbench Verification Suite consists of three modular products available as an integrated solution for generating test benches or separately to integrate with existing capabilities. Two new products, Quickbench Manager and Quickbench Sequencer, join Quickbench Modeler, an enhanced version of the current Quickbench 2.1. Quickbench Manager manages test bench data and the test bench generation flow. Quickbench Modeler automates the design and generation of the structural and timing specifications of test benches, and Quickbench Sequencer automates the design and generation of verification stimuli. Interface design occurs in Quickbench Modeler's graphical timing diagram editor. The bus-functional model test bench components are generated from the timing diagram specifications, which can be understood and modified for future use. The suite will be available in September on Sun and HP workstations and Windows 95 and NT PCs. Pricing for Quickbench Modeler and Quickbench Sequencer start at $15,000 each for a single-language, floating license. Quickbench Manager costs $5,000. Customers who are currently on maintenance for Quickbench will receive an upgrade to Quickbench Modeler and Quickbench Manager at no charge. Chronology Corp., Redmond, Wash. Contact (800) 800-6494 or www.chronology.com.

Cores Digital and mixed-signal IP for the consumer, communications, image processing, and security markets is now available from Xentec, including JPEG codec and DCT/IDCT soft cores and triple 8-bit DAC and USB transceiver driver hard cores. The predefined, preverified soft cores include documentation, synthesis scripts, and a test bench. Many of the cores include a system-level test bench, functional simulation model, and test vectors. The triple 8-bit DAC and USB transceiver are currently targeted to a 0.35-µm triple-layer-metal CMOS process. The company's Design Services Group can retarget the cores to any process with adequate lead time. The soft cores are available in Verilog and VHDL. Individual cores will be available in Q3. Xentec, Inc., Oakville, Ont. Contact (888) 7-XENTEC or www.xentec-inc.com.

FPGA support Version 2.1 of both FPGA Express and FPGA Compiler II offers new device support for major FPGA and CPLD vendors. The tools also include initial VHDL 93 support and a number of enhancements, such as functional simulation output capability. FPGA Express 2.1 supports eight new FPGA and CPLD architectures recently introduced to the market and is available through the Synopsys Viewlogic Systems Group. Pricing starts at $4,995. Existing customers with support contracts will be upgraded at no additional cost. FPGA Compiler II version 2.1 is available for $16,500 to existing customers. Synopsys , Inc., Mountain View, Calif. Contact (650) 962-5000 or www. Synopsys .com.

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integrated system design  August 1998