Tools and Technologies Products and services for IC and electronic system design

Tools and Technologies

FPGA design Designer Series RS-1998 ensures timing analysis accuracy--helping designers work at an internal clock rate in excess of 320 MHz--by reporting pin-to-pin timing delays between modules instead of lumping routing delays and module delays together. A flip-flop report facilitates accurate prediction of device utilization by determining the number of sequential and combinatorial macros used in a design. Refinements to the ACTmap include clock resource checking and speed and utilization performance improvements. Also refined is ACTgen, which provides a new user interface, new macro types, behavioral VHDL and Verilog model generation capability, and improved reporting. The software is available now for $995, and existing customers who have a valid maintenance contract will receive a free upgrade. The Designer Lite version of R2-1998 is available free from the company's Web site. Actel Corp., Sunnyvale, Calif. Contact (408) 739-1010 or www.actel.com.

DRAM simulation model The Memory Modeler now supports dual data rate (DDR), an emerging DRAM memory architecture. The tool aids in model creation and the design of new memory components for chip and system verification through its class-based software architecture. Memory Modeler includes support for both VHDL and Verilog and runs under Windows 95 and NT, SunOS, Solaris, and HP-UX. It's priced at $5,000 and up, including models. Denali Software, Inc., Palo Alto, Calif. Contact (650) 325-7241 or www.denalisoft.com.

FPGA software Version 1.5 of the Foundation Series tool suite contains enhancements for mainstream programmable logic designs. The latest release includes the new AKAspeed technology, a suite of algorithms and algorithmic strategies combined with new feature sets and applications. The software offers single push-button design flows; key elements of the Foundation Series--Express are Synopsys 's FPGA Express synthesizer and advanced implementation tools--such as HDL and state machine editing, graphical timing constraint entry, and synthesis timing analysis--embedded directly within the project manager, eliminating the need to invoke the tools individually. It supports all of Xilinx's product families and runs under Windows 95 and NT. Pricing starts at $95 (Foundation Series­Base). Xilinx, Inc., San Jose, Calif. Contact (408) 559-7778 or www.xilinx.com.

Wireless support Systemview2.1 provides additional modeling, analysis, and debugging features for the simulation and testing of complete wireless communication applications at the system level. Enhancements to the tool suite include a three-channel system probe that allows a designer to trace a signal through an entire system by moving the probe to the output of each block during system execution, thereby pinpointing the source of the problem in real time. Systemview 2.1 configurations start at $3,495, available on Windows 95 and NT platforms. Existing customers under maintenance can download the new version from the company's Web site at no charge. Elanix, Inc., Westlake Village, Calif. Contact (818) 597-1414 or www.elanix.com.

FPGA development software Version 9.0 of the Max+Plus II programmable logic development software supports Altera's new 0.25-µm Flex 10KE device family, which offers 66-MHz in-system performance and densities of up to 250,000 gates. The software also supports Altera's new Fineline BGA packages, which require less than half the board space of the standard BGA packages currently employed for programmable logic. Timing-driven compilation algorithms in the software improve design performance an average of 10 percent over the previous release. Version 9.0 also introduces Jam byte code, a compiled representation of the Jam programming language, which reduces average in-system programming time by 25 percent and also reduces the total time that boards stay on automatic test equipment or programming hardware. It is available now for PCs, starting at $995. All Altera customers currently on active maintenance will receive an upgrade at no additional cost. Altera Corp., San Jose, Calif. Contact (800) 9-ALTERA or www.altera.com.

PowerPC driver tool Driveway-MPC850 automates the creation of USB and other device drivers for the Motorola MPC850 family of embedded PowerPC processors. It allows developers to integrate Motorola's integrated processors into their LAN-to-WAN internetworking products. The tool runs under Windows 95 and NT and integrates with RTOSs and compiler tools. Pricing starts at $29,500. Aisys, Inc., Santa Clara, Calif. Contact (408) 327-8820 or www.aisysinc.com.

Linux tool kit The GNUPro Toolkit is now available for use with the Red Hat Linux operating system. It provides C compilation and language enhancements supporting the proposed C++ standard. The tool kit includes access to open source code and portability among host environments for application migration. In addition to the gcc compiler, it features g++, providing language support for the proposed ANSI C++ standard; and gdb, a source- and assembly-level debugger, including the GDB graphical user interface. GNUPro also offers cross-platform capabilities and support on other major operating systems, including Windows 95 and NT, Solaris, SunOS, HP-UX, AIX, and Irix. Pricing starts at $7,495 and includes a one-year support contract for up to five developers. Cygnus Solutions, Sunnyvale, Calif. Contact (800) CYGNUS-1 or www.cygnus.com.

ECIX tools The ECIX Toolkit CD-ROM aids in the development of new software products based on the Electronic Component Information Exchange (ECIX) standards and specifications. The free CD-ROM includes standards documentation, collateral, sample data, and software. Silicon Integration Initiative, Inc., Austin, Texas. Contact (512) 342-2244 or www.si2.org/ecix.

Reliability simulator Glacier, jointly developed by Matsushita Electric Industrial Company and BTA Technology, predicts circuit timing degradation and balances performance and reliability. It automatically characterizes library cells, considering hot-carrier effects; generates aged timing information; and analyzes performance shifts from initial characterization. It works with commercially available EDA environments and supports Verilog simulators, Detailed Standard Parasitic Format (DSPF), and Standard Delay Format (SDF). Glacier is available now for $100,000 and up. BTA Technology, Inc., Santa Clara, Calif. Contact (408) 986-1011 or www.btat.com.

Programmable logic tool ISPHDL System for Synplicity facilitates high-density ISP device design. The system features Synplicity's Synplify VHDL and Verilog synthesizers integrated with the ISPDS+ HDL Synthesis-Optimized Logic Fitter v5.2. It contains a multilevel-timing-constraints management system, a built-in language-sensitive editor, and an optional graphical (block diagram) analysis tool that gives direct feedback for design debugging. Running on a PC platform, it's priced at $995 for the base version, which supports the ISPLSI 1000E, 2000, 2000V, and 3000 families. For an additional $2,500, users can upgrade to the unlimited-capacity advanced version that supports the ISPLSI 6000 family. Both versions are available now. Lattice Semiconductor Corp., Hillsboro, Ore. Contact (503) 681-0118 or www.latticesemi.com.

HDL design purifiers Verilint 5.0, a Verilog code purifier, handles large designs and can process up to 5,000 lines of RTL code per second. New semantic checks have been added, bringing the total to over 600. VHDLlint 2.0, a VHDL code purifier, provides a revised GUI and source navigator, improved performance for large designs, and additional language checks for synthesizability. VHDLlint 2.0 and Verilint 5.0 are available immediately. Pricing ranges from $9,500 to $44,500. InterHDL, Inc., Los Altos, Calif. Contact (800) 884-7371 or www.interhdl.com.

Design validator EDAvalidator 2.0, an automated system design validator, alleviates data consistency problems in engineering, design, and manufacturing. The new version adds a Windows look and feel, expanded intertool communications, and enhanced inference engines. It works interactively or in the background as an automated part of the design process, includes clear visual guides for interactive use, and creates concise reports when used in a batch process. Available now, the tool comes in a range of configurations that run on Unix and Windows NT platforms. The average first-seat price is $40,000. Xynetix Design Systems, Inc., Fishers, N.Y. Contact (800) 334-0663 or www.xynetix.com.

Windows EDA tool Renoir '98 is fully compatible with Windows NT and 98. The graphical design environment supports Object Linking and Embedding (OLE), allowing users to drag and drop any Renoir diagram, even from the desktop, into any OLE application. The automated uninstaller ensures that core components or shared components necessary to other applications are left intact. Long file names also are supported. Year 2000­compliant, Renoir '98 starts at $3,000; runs under Windows 95, 98, and NT, as well as under Solaris and HP-UX; and supports extra plug-in interfaces to Cadence's Verilog-XL and Leapfrog, Exemplar's Leonardo-Spectrum, Mentor Graphics' Monet, Model Technology's Modelsim, and Synopsys 's Design Compiler and FPGA Express. VHDL and Verilog support, together with all interfaces, are included at no extra charge. A fully functional free evaluation version can be downloaded from www.renoir.com. Mentor Graphics Corp., Wilsonville, Ore. Contact (800) 685-7000 or www.mentorg.com.

Design migration software The latest version of Design Rule Enforcement and Migration software facilitates reuse and optimization of silicon IP for deep-submicron design. The new release offers improved speed and reduced setup and overall migration time, and it includes a new device-resizing feature for more optimized designs. DREAM handles memory blocks of more than a million transistors, up from 400,000 transistor blocks. It facilitates reuse and optimization of cells, memories, blocks, and now full chips from one process design rule to another. New functionality has been added for better handling of memories, accelerated migration, and device resizing. An improved wire length optimizer offers faster run times and decreases migration time. Faster layer arithmetic makes setting up the migration flow easier, accelerating run time. DREAM is available on SunOS, Solaris, and HP-UX operating systems and is priced at $175,000 and up. Sagantec, Milpitas, Calif. Contact (888) SAGANTEC or www.sagantec.com.

Project data manager Personal PDM promotes work-in-process management for users of Accel EDA electronic system design software. It manages all data through a product's life cycle, ensuring secure data storage and transmission using a single-user, owner-protected vault. Project templates are included. AutoCAD native files can be loaded and read into the PDM database. Personal PDM uses the Adobe Acrobat Reader to view and print any file type--including those of Accel EDA, Microsoft Office, and AutoCAD--in .pdf format. There's no per-seat charge for viewing files in a Web-centric environment. It operates on Windows 95 and NT. It's priced at $2,500, and is available now. Accel Technologies, Inc., San Diego, Calif. Contact (800) 488-0680 or www.acceltech.com.

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integrated system design  October 1998