Tools and Technologies Products and services for IC and electronic system design

Tools and Technologies

Formal verification tools The Tuxedo family of formal verification tools includes Tuxedo-LEC, a logic equivalence checker, and Tuxedo-LDD, a logic debugging and diagnosis tool. Tuxedo-LDD automatically identifies and displays error candidates. It includes built-in capabilities for the designer to specify constraints to explore the differences. It also automatically generates on-line schematics for graphical debugging and provides linking between RTL source and the gate-level design. In the Tuxedo-LEC equivalence checker, correlation learning technology explores the structural and functional relationships between golden and revised designs. The algorithms used in correlation learning help improve processing speed and better utilize system memory resources. The tool's comparison engine uses multiple techniques to compare the equivalence of two designs. The key-point mapping algorithm automatically identifies the correspondence of key points by examining their functional relationships. Both tools are available now for Verilog. Tuxedo-LEC costs $80,000; Tuxedo-LDD costs $25,000. Verplex Systems, Inc., Santa Clara, Calif. Contact (408) 983-9800 or www.verplex.com.

State machine coverage The Coverscan/Statescan Verilog code coverage tool now features automatic state machine extraction and paired state machine coverage capabilities. It's available now for $15,000. The company provides the new features and enhancements to customers as part of its ongoing maintenance support. Design Acceleration, Inc., San Jose, Calif. Contact (408) 885-1885 or www.designacc.com.

Automatic memory verification The Autotest automatic verification software facilitates instant validation of models created with memory modeling software. It automatically generates test vectors for specific memory components or cores through an extension to Denali's proprietary class-based memory modeling architecture. Test benches generated using the software perform complete functional tests of the model, along with positive and negative timing checks. The tool, available now as an option to Memorymodeler, starts at $10,000 and runs under Windows 95 and NT, SunOS, Solaris, HP-UX, AIX, and Irix. Denali Software, Inc., Palo Alto, Calif. Contact (650) 325-7241 or www.denalisoft.com.

LVS verification tool The latest release of LVS includes a new text editor that allows designers to view multiple netlist, element description, prematch, element and node list, and output files simultaneously. A new queuing feature allows multiple runs to be set up and edited within the LVS environment. Available now, the tool runs on Windows 95, 98, and NT and costs $3,995 or, as part of the layout and verification package L-Edit Pro, $12,995. Tanner EDA, Pasadena, Calif. Contact (626) 792-3000 or www.tanner.com/eda.

Boundary-scan test and programming Version 2.3 of Asset's boundary-scan test and programming system includes two new products, ISPextender and QuickISP, which expand options both for test engineers who are adding ISP capabilities to boundary-scan test stations and for engineers who need only to program devices. ISPextender, an optional software module to the Scandriver product, can help make a manufacturing process more efficient by performing both test and in-system programming on the same station. QuickISP is a tool for users who are interested only in programming devices and don't need the array of boundary-scan test capabilities in the test and programming system. It features a Windows-based graphical user interface. Version 2.3 also supports new hardware options for users. Besides running from its own PC, PCMCIA, and VXI hardware cards, it will now run from DSP emulation hardware manufactured by White Mountain DSP and Texas Instruments. The new release will be shipped to customers currently under a maintenance contract. ISPextender is priced at $2,495, and QuickISP at $4,995, in addition to the cost of one of Asset's hardware options that can be purchased separately. Asset Intertech, Inc., Richardson, Texas. Contact (972) 437-2800 or www.asset-intertech.com.

PCB design applications Release 9 of OrCAD Layout Plus, OrCAD Layout, and OrCAD Layout Engineer's Edition includes reorganized menus and dialogs that follow the flow of the PCB design process, and a built-in interface to Cadence's Specctra products. New manual routing functionality includes true T-routing, support for free vias, improved support for ball grid arrays, and support for microBGAs. OrCAD Layout Plus is $9,995, OrCAD Layout is $6,995, and OrCAD Layout Engineer's Edition is $2,995. OrCAD, Inc., Beaverton, Ore. Contact (800) 671-9505 or www.orcad.com.

Free libraries Free library offerings have been extended to customers of the UMC Group, which has licensed Artisan's 0.25-µm and 0.18-µm memory generator, standard-cell, and I/O library products. Under the agreement, UMC's customers will now receive Artisan's library products directly from the library creator at no cost. Artisan will offer free direct technical support for all of UMC's customers and work with UMC to design, optimize, and validate Artisan's Process-Perfect libraries for UMC's semiconductor process. Preliminary design kits for the UMC 0.25-µm process are available today. The complete library, consisting of Artisan's single- and dual-port memory generators, standard-cell library, and I/O library, is expected to be available by year's end. Preliminary design kits for the UMC 0.18-µm process are also expected to be available at that time. Artisan Components, Inc., Sunnyvale, Calif. Contact (877) 278-4542 or www.artisan.com.

Test set simulator Testify, a simulation manager for the development of mixed-signal board- and system-level test program sets, guides the test engineer through the process of inserting faults into a unit under test (UUT) and determining how well a test program will function in detecting those faults. It uses the Saber mixed-signal simulator and Mast hardware description language along with Analogy's Inspecs Pro analysis tools to provide test engineers with information on fault behavior of the UUT and effectiveness of proposed test programs. The simulator allows the test engineer to analyze UUTs under normal operating conditions, then insert and process faults. Existing Analogy customers who are already using Saber can purchase Testify as a separate option. Testify Pro includes Saber, the Saberscope waveform processor, Inspecs Pro, and Testify. It also includes a choice of schematic capture software: either Analogy's Sabersketch design editor or a Saber Frameway Interface to Mentor Graphics', Cadence's, or Viewlogic's schematic capture products. Testify and Testify Pro are currently available for Solaris, HP-UX, and Windows NT. Testify is $35,000, and Testify Pro is $94,900. Analogy, Inc., Beaverton, Ore. Contact (503) 626-9700 or www.analogy.com.

DSP simulation suite The revised DSP Workshop adds support for frame-based processing in the DSP Blockset, allowing users to process blocks of data as well as individual data samples within a time-driven simulation. As a result, Simulink users can now simulate DSP designs at speeds previously available only in data flow simulators, while allowing a more natural mapping to real-time implementation. The re-architected DSP Blockset makes use of the new infrastructure in Simulink 3 for use in real-time speech, audio, and communications applications. Each block now automatically adapts to the incoming signal's data type, sampling rate, and frame size. The enhancements reduce the size of simulation models and generated real-time code and eliminate the task of manually verifying the properties of each individual block. Further additions to Simulink include new usability and scalability features. Simulink 3 contains complex data types, sample-rate propagation, and support for multirate systems, as well as simulation of large-scale communication systems. DSP Blockset 3 includes over 50 new blocks that support linear algebra, spectral estimation, multirate filters and filter banks, and an expanded set of fundamental computational and control operations, allowing users to move Matlab-based algorithms directly into simulations that mirror the operation of the DSP processor and map to the real-time implementation. In the Signal Processing Toolbox 4.3, the graphical user interface now supports improved visualization of filter designs, including a pole-zero editor. The DSP Blockset's filter realization wizard now supports fixed-point FIR filters of any word length up to 128 bits when the optional Fixed Point Blockset 2 is installed. DSP Workshop runs under SunOS, HP-UX, AIX, and Windows 95 and NT. Pricing starts at $5,900 and varies depending on location, platform, and configuration. The Mathworks, Inc., Natick, Mass. Contact 508-647-7000 or www.mathworks.com.

Verilog rule checker Rulechecker, an addition to Logiscope C for Windows, checks Verilog coding, naming conventions, and presentation rules. It provides information on a violation, locates the anomaly, and offers suggestions to make the code comply with standards. In addition to the 50 predefined rules delivered with the product, users can modify, create, and integrate custom programming rules. The open tool is constructed around an API that provides access to all the information a program contains. It allows organizations to standardize coding practices by integrating the rules specific to the individual company or project. It provides a presentation of each rule included in the package, giving explanations and reasons for its use, its scope and limitations, and instructions required for using the rule efficiently. Automatic self-checking in interactive or batch mode sorts results by severity, by file, or by rule, and a text editor can localize rule violations in the source files. Rulechecker for Windows 95, 98, and NT costs $2,400. A Unix version is also available. Verilog, Inc., Dallas. Contact (800) 424-3095 or www.verilogusa.com/solution/logiscop.htm.

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integrated system design  November 1998