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Could EDA Roadblocks Derail Moore's Law? Engineers need tools that meet the demands of deep-submicron circuit design. by Jim McCanny

Doomsayers are claiming that Moore's law--the well-known maxim proposed by Intel's Gordon Moore that the number of transitors on a chip will double every 18 months--may soon fail because of our inability to build circuits in process technologies under 0.1 µm. These pessimists may be right, but they could be wrong about its cause. The roadblock may lie not in our manufacturing abilities, but in our EDA tools.

Leading-edge chips have always stretched current EDA tools to the limits. Fortunately, these designs are typically larger memories or faster processors that, in production, alleviate many of the problems that arise in their implementation. As a result, the rest of the design community has been able to design larger and larger chips without facing any major EDA hurdles.

In the era of deep-submicron (DSM) design, however, many factors affect design productivity. Such DSM effects as interconnect parasitics and coupling capacitance have given rise to the need for more detailed analysis in the design flow. Compounding the problem is the increased number of transistors that we can now squeeze onto silicon. Today's design flow has more steps and more iterations and requires designers to have more detailed knowledge of DSM effects.

The complexity of DSM design tests the quality of EDA tools. Current designs require the tools to handle 10 to 50 times the data of the smaller designs of the past, when EDA tools didn't really address interconnect. Back then, interconnect was treated simply as a lumped capacitance that only required a few bytes of storage per net. Now, distributed RC networks have resistance and capacitance for every node, and a single net can have hundreds or thousands of nodes. The storage and analysis of this data is a major roadblock to Moore's law. Run-time analysis of postlayout netlists can be 10 or even 100 times greater than that of prelayout netlists.

Using parasitic reduction, designers can reduce the data by as much as 90 percent with little or no loss of accuracy; however, many parasitic reduction techniques are unable to handle the complexity (meshes and loops) and capacity (millions of RCs on a single net) of DSM interconnects. Even though improved techniques such as using scattering parameters can solve those issues, it is better to address them during extraction.

Current RC extraction tools use decomposition, which cuts nets into many small RC segments using geometric relationships and Boolean rules to determine where to break the layout. This method, however, generates superfluous data and introduces errors at the boundary of each cut.

A better solution is to break the nets into medium-sized pieces in a way that minimizes boundary effects. By coupling a smart cutting technique with a 3-D approach, we can extract highly accurate and compact RC networks. Add to the mix "on-the-fly" parasitic reduction of subnetworks and designers will be better equipped to control the generation of parasitic data. This method may not completely solve the problems associated with handling the DSM data explosion, but learning how to tackle the challenges of DSM design will help us get back on track with Moore's law. *

Jim McCanny is the executive vice president of Ultima Interconnect Technology, Inc. (Sunnyvale, Calif.).

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integrated system design  January 1998