Viewpoint

Hot Carrier Effect--A Fading Concern or a Growing Problem? For deep-submicron technologies, performance goals and reliability constraints represent two opposing concerns. Reliability simulation is needed to carefully weigh the trade-offs and provide a solution for current and future designs. by Zhihong Liu

When the power supply voltage was dropped from 5 V to 3.5 V, many people thought that the hot carrier effect would disappear. Surprise! The hot carrier effect is a greater concern today than ever before, and the problem is growing. It's interesting to examine the reasons for this trend and what can be done about it.

Difficulties are increasing because of the nature of the hot carrier effect. As the electrons pass through the high electric field region at the drain junction, they become so energetic (hot) that they can damage the oxide/silicon interface. That can cause threshold voltage shifts, carrier mobility decreases, and reduced circuit speeds.

To suppress those effects, lightly doped drain (LDD) was introduced in the early '80s. Unfortunately, LDD exacts a price in transistor current and speed. Nonetheless, it's necessary even for new technologies with reduced supply voltages. That's because shorter channel lengths, thinner oxide, and shallower junctions all raise the electric field in the channel despite the low voltage.

The demand for higher performance is forcing semiconductor companies to maximize transistor current and speed at the expense of hot carrier reliability. But how much have hot carrier reliability margins decreased in the last several years? In the early '90s, semiconductor companies almost universally guaranteed 10-year transistor lifetimes under constant DC stress. That means that within 10 years, transistors will have less than a 10 percent decrease in I _d at low V _ds (the percentage loss of I _d is larger at a low V _ds than at a high V _ds ). Today, companies only guarantee a few months (or even less) of lifetime under DC stress, and that is for I _d at V _ds = V _DD . The justification is that transistors suffer a much smaller equivalent DC stress time under real circuit operation.

Unfortunately, all transistors in a given design don't experience the same degree of stress. Some will fail before others. Furthermore, not all circuits and devices operate at one particular bias. The result: actual average current degradation and transistor speed losses are greater than anticipated.

Other new trends also put circuit reliability at increased risk in new technologies. The PMOSFETs, which used to become faster after stress (thus partially counteracting the speed loss of NMOSFETs), also suffer speed loss. Most importantly, voltage overshoot in fast circuits can reduce hot carrier lifetimes by more than an order of magnitude, depending on circuit topology, coupling capacitances, and rise and fall times.

Hot carrier simulations can help to evaluate circuit reliability more precisely. Without reliability simulations, there's no way to map the precise extent of degradation and uncover which parts of the circuit will fail before others. Hot carrier simulations can help for all types of circuits: large or small circuits, handcrafted or standard-cell, digital or analog. Not adopting this new technology will lead to one of two consequences--questionable reliability or suboptimal performance.

CAD has been a powerful and indispensable technology for IC design. No one would dream of designing a circuit without using CAD tools to verify its functionality and performance. Isn't it time that the IC industry apply the enormous benefits of CAD to verify circuit reliability? *

Zhihong Liu is president of Berkeley Technology Associates (Santa Clara, Calif.).

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integrated system design  February 1998