Viewpoint

Cost or Performance--ASICs Still Beat FPGAs Despite technology advances, gate arrays and standard cells still outperform FPGAs and cost significantly less in high volumes. by Vince Hopkin

Recent debate has raged about whether or not FPGAs are reasonable substitutes for ASICs in terms of cost and performance. At American Microsystems, we think the answer is no. The true cost differences between ASICs--both gate array and standard-cell designs--and FPGAs are large, especially for gate counts greater than 5,000.

FPGA companies are promoting their ability to meet cost points equal to an ASIC based on today's technology capabilities and the fact that approximately 50 percent of the designs are pad-limited. The argument goes like this: If a device is pad-limited, the die size is the same for an FPGA as it is for an ASIC, thus making the cost the same.

But the pad-limited argument only scratches the surface. There are actually two contributors to the cost of silicon: area per gate and the cost of silicon manufacturing, which in turn has two components, the number of required masking levels and whether fabrication is internal or external.

Area per gate is a derivative of whether the design is core-limited (that is, the die size is driven by gate density) or pad-limited. For core-limited designs, ASICs are more-cost effective because of the area-per-gate benefits of an ASIC architecture. If the design is pad-limited, then the FPGA die size is basically the same as a gate array or standard-cell design.

With regard to the cost of manufacturing, ASICs are clear winners on both counts. Masking levels add $50 to $70 per level to the cost of processing a wafer. Gate arrays and standard-cell ICs generally require between 10 and 14 masking levels to manufacture a finished product. But because of the programmability requirements at the device level, FPGAs typically require 15 to 20, driving up the cost significantly.

As for the other element of the cost of manufacturing, most ASIC suppliers do their own manufacturing, but for FPGAs, almost all vendors use foundries. Naturally, if the supplier does its own manufacturing it cuts out the middleman and saves 30 to 50 percent in the cost of a wafer.

Beyond cost, there are other factors to consider in choosing an FPGA or in converting an FPGA design into an ASIC: performance, volumes, and the experience of the ASIC supplier.

FPGA suppliers are using performance as a point of comparison with ASICs. The bottom line is that for core performance requirements demanding fast gate delays and high-speed clock frequencies, the ASIC is much faster, thanks to the basic differences in architecture. FPGAs are getting faster with smaller geometries, but so are ASICs, so the gap isn't narrowing as much as FPGA vendors would like to claim.

Another key factor in performance is power consumption. The higher the performance for the FPGA, the higher the power consumption--two to three times higher than an ASIC with comparable performance.

Volumes are another important consideration in choosing between an FPGA and an ASIC or in deciding whether to move a design from an FPGA to an ASIC, since NRE is a consideration with ASIC designs. If the total device cost, including NRE, is less than the FPGA cost, customers should look at converting to an ASIC.

A risk assessment of the ASIC supplier's translation capability also should be done. Tying up a design engineer for months on an FPGA-to-ASIC conversion isn't necessary with an experienced ASIC supplier that has converted hundreds of FPGAs and can make the process fairly painless. Vectorless services are also becoming available, making FPGA-to-ASIC conversions even more painless for the customer.

When all is said and done, beyond prototyping gate arrays and standard-cell ICs still offer a clear advantage over FPGAs in both cost and performance. ASICs will continue to provide a clear-cut cost reduction path for customers needing the most competitive solution in production volumes.

To voice an opinion on this or any Integrated System Design article, please e-mail your message to miker@isdmag.com.

integrated system design  March 1998