Viewpoint

Code Coverage: 'Go with the Flow' It's just not prudent to gloss over coverage questions when commercial code coverage tools are so well proven and available as integral components of the overall design flow. by Surrendra Dudani

Now Verilog designers can have the advantage of thorough, high-performance code coverage operating in the background with every simulation run, providing them with reliable, comprehensive metrics with which to gauge test case effectiveness. How important is this capability? For the early discovery and resolution of design problems, it's all important.

Early implementations of code coverage, first appearing just two years ago, imposed a high overhead on the simulation process. The technology represented a new philosophy in test case assessment, and few initially appreciated the value and use of the coverage data provided. In addition, the earlier adopters of code coverage had to use it very sparingly at first because, given that the simulation overhead with first-generation code coverage tools ran from 500 to 1,000 percent or more, they couldn't afford to check an entire design.

In stark contrast with those early results, recent benchmarks have demonstrated that complete statement coverage, the most widely used of the coverage types, can be achieved with a simulation overhead in the range of 10 percent, an acceptable performance hit for the advantages of coverage information, according to many users. With code coverage, all personnel in the verification process benefit in terms of design confidence, from designer to verification engineer all the way to the ASIC vendor, where process engineers are now recommending code coverage to their customers.

Breadth of code covered has improved dramatically as well, with users able to assess the behaviors of their designs clear down to multiple interacting state machines, determining the states exercised, the arcs traversed between states, legal and illegal transitions, data transfers within buses, and other difficult-to-assess characteristics of the design and test cases under analysis.

Finally, the ease of use of code coverage tools has improved markedly with the availability of graphical user interfaces. These interfaces enable users to rapidly, almost intuitively navigate code coverage results accumulated through regression testing of their designs.

Consequently, the missionary period for HDL code coverage is behind us, and it's no longer the exclusive province of power users. Instead, code coverage is now understood and used by a broad cross-section of the design and verification community. While small design houses amortize these new tools over just a few projects, large corporations are already securing site licenses and modifying their design flows to provide the benefits of code coverage to all their design and verification staff.

I predict that very soon the leading ASIC vendors will use code coverage as a screen for incoming designs to ensure adequate testing by their customers before they will even accept designs for fabrication.

Code coverage has already found an enthusiastic reception in the emerging IP business segment. IP suppliers are extremely conscientious in providing known, reliable modules that will be incorporated into higher-level designs. A number of them have already embraced code coverage so that they can supply coverage metrics as part of their total quality assurance package.

Everybody wants first silicon success and no tool is equal to the challenge standing alone. Code coverage really complements the simulation and verification process and can be considered a trusted shortcut to improved confidence in designs. With the increase in use, from in-house designers through design and fabrication service providers, through IP cores, and elsewhere, code coverage is likely to become more tightly coupled with other verification tools and to be offered in the future as part of larger, more integrated verification solutions.

Now with dramatically improved throughput, increased breadth of functionality, interfaces to accommodate both advanced and casual users, the code coverage logjam is definitely broken, and the design flow will continue to pick up speed accordingly. It's high time to "go with the flow."

Surrendra Dudani is the director of R&D for the EDA Products Division of Advanced Technology Center in Waltham, Mass. He has worked at the leading edge of the verification field since 1984 and is the chief architect of Covermeter, a leading Verilog code coverage tool. He earned his Ph.D. in computer engineering at Syracuse University with a dissertation on hardware description languages and design environments.

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integrated system design  April 1998