Viewpoint

The New 'ASIC Replacement' FPGAs FPGAs have come a long way. Crucial to reducing time to production, they will soon dethrone gate arrays as the preferred production technology. by Bob Sandler

The ASIC industry's belief that gate arrays are always more cost-effective than FPGAs in production is about to be dismantled. Case in point: Vince Hopkin's argument that gate arrays still offer a "clear advantage" over FPGAs in volume production ["Cost or Performance--ASICs Still Beat FPGAs," March] ignores today's most important factors determining product success: fast time to production and a high quality-to-cost ratio.

Because today's product life cycles are so brief (12 to 18 months), time to production becomes essential, which means that programmable logic assumes a more critical role than ever in the rapid prototyping of products and moving them quickly into full production.

With in-system reprogrammability, FPGAs demonstrate faster design time than any ASIC technology. In fact, reprogrammability virtually eliminates prototype turnaround time. Rapid prototyping facilitates concurrent hardware/software and real-time debugging. Concurrent engineering eliminates the weeks of waiting time that's required for prototypes, which are needed to complete software verification. Because certain FPGAs are 100 percent factory-tested, the usual scan insertion and test vector generation services are unnecessary. That often reduces development time by over one half.

After development and beta testing, sales channels must be quickly stocked for the initial customer demand. Because programmable logic typically has a zero- to four-week lead time for production quantities, market penetration is immediate. With the standard ASIC 8- to 16-week production delivery schedule, a two- to four-month sales delay substantially affects market acceptance, revenues, and profits. Recall the findings of that well-known McKinsey study: A six-month delay costs a company one third of its profits.

Addressing the quality and performance issue, programmable logic's process technology has recently surpassed that of gate arrays. Although FPGAs have historically lagged the ASIC industry by one or two generations, current production FPGAs are fabricated with 0.35- and 0.25-µm processes. FPGAs introduced later this year will use an advanced 0.18-µm process. Because larger FPGAs contain more transistors than Pentium II microprocessors, independent wafer foundries have been using these complex FPGAs to debug new fab processes, replacing previously used DRAMs.

Gate arrays, on the other hand, incur a large penalty by migrating to deep-submicron technologies. The majority of timing delays in deep submicron now come from interconnects, not logic gates. Minimizing interconnect delay requires adding metal layers to create more routing resources. Unfortunately, each additional metal layer adds considerably to mask and wafer fab costs and also extends the prototype turnaround time.

New, lower-cost FPGAs benefit from technology advances to increase performance and densities while reducing die size. In the past, a larger die size had limited price competitiveness. However, the smaller-die "ASIC replacement" FPGAs are highly reproducible while providing all the reprogrammability and production flexibility of traditional programmable logic.

Newer FPGAs incorporate such ASIC-like features as configurable on-chip RAM and support the most popular operating frequencies of 33 to 75 MHz or higher. Also, they use low-cost plastic packaging and a streamlined test methodology. The cost savings and smaller dice have thus leveled the playing field and allowed FPGAs to compete directly with gate arrays.

If a design change or fix is needed in silicon, the ASIC inventory may not be usable and may be scrapped. FPGAs eliminate the risk of discarding inventory and work in progress. Thus they also lower the penalty of an inaccurate sales forecast.

The new low-cost FPGAs and today's rapidly changing market conditions therefore have raised the criteria to justify ASIC-to-FPGA conversions. What's more, keep in mind that today's FPGAs support standard Verilog and VHDL design flows that help such a transition for ASIC designers.

It's clear that if ASIC users consider competitive pricing, time to production, and the cost of conversion, FPGAs will become the preferred alternative for most designs.

Bob Sandler is ASIC replacement marketing manager at Xilinx, Inc. in San Jose. 7X

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integrated system design  August 1998