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Topology before Synthesis Topology planning is essential to solving interblock interconnect problems, as well as key to reducing costly iterations. by Rod Dudzinski

The burgeoning number of purchased and internally developed IP blocks contained within system ICs, combined with shrinking process technologies, has created new design barriers that are rooted in interblock interconnect problems. Thus, in the same way that gate-level design tools evolved to address issues that weren't solved by transistor-level design tools, block-level design tools must in turn emerge to overcome system IC design obstacles not addressed by gate-level tools.

System IC design must incorporate a block-level topology plan. Such a plan, or "topology blueprint," is the exact physical configuration of a chip as determined by the shapes, areas, port layers, and locations of the blocks, and also the interconnect structures. Additionally, it includes the chip's timing and signal integrity requirements. Why use the term "blueprint?" Like any blueprint, a block-level topology blueprint would map out a high-quality routable design that meets design objectives and avoids deep-submicron timing and signal integrity violations.

Block-level topology planning must be initiated early in RTL design--specifically during functional partitioning and micro-architectural design, when the designers have the largest impact on performance and area. Tools focused on interblock interconnect planning, then, would be used before tools for intrablock functional design.

Current design methods employ a sequential "construct, then evaluate, then repair" approach that includes RTL design, RTL floorplanning and logic synthesis, physical floorplanning, and placement and routing. Although RTL floorplanning can reduce iterations by improving the links between gate-level synthesis and gate-level detailed placement, that convergence generally occurs late in the design cycle. Thus the user must have a fully synthesized and placed netlist delivered in order to obtain preliminary timing and area estimates. By then it may be too late in the design process to influence the RTL design, especially those micro-architectural decisions that have the largest impact on performance.

Additionally, floorplanning tools typically don't accurately account for routing resources, power, clocks, or buses, forcing designers to construct floorplans manually and then complete the routing to fully assess whether timing, noise, and area objectives can be met. A single iteration on a new floorplan can take 3 to 10 days. Each iteration is so expensive that normally only one or two floorplans can be analyzed for trade-offs, with the remaining time spent on optimizing results.

Topology planning should precede logic synthesis and gate-level floorplanning, which are best suited for intrablock design. That approach would eliminate time-consuming manual interconnect correction iterations performed late in the design cycle by, first of all, providing accurate prelayout interblock wire delay estimates to better achieve system-level timing goals. Second, the approach would allow designers to add block-level power, clock, test, and signal bus interconnect before block construction. Third, it would prevent designers from inadvertently locking themselves into the wrong implementation path, only to find out later that their timing, area, power, test, and packaging design objectives can't be met. Finally, the approach would more easily accommodate the concurrent design of individual blocks with overall system design.

Given the rapidly growing number of blocks in system IC designs, it's imperative that designers have access to block-level topology planning tools. Viable tools will require new block-level algorithms to handle nonuniform elements, substantially longer wire lengths, n levels of metal, different extraction mechanisms, and highly structured wiring patterns. Automatic multilevel hierarchy manipulation would assure designers that overall physical requirements are met across levels of hierarchy. The tools also need close ties to the final interconnect implementation.

For system ICs, topology before synthesis would greatly reduce design cycles by reducing the numerous manual iterations to obtain an optimal block-level topology and interconnect design.

Rod Dudzinksi is a cofounder of Aristo Technology, Inc. in Cupertino, Calif., where he's now vice president of marketing. He has over 16 years' experience in the EDA and IC industries, having worked for Fujitsu Microelectronics, Cadence Design Systems, and Cooper and Chyan Technology. 7X

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integrated system design  September 1998