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Test: The Other IP Without equal attention to test IP, chip makers will lose the time-to-market advantages offered by design IP. by David Flaningam

Just as IC designers need to reuse existing cores to quickly develop sophisticated designs, test engineers need to reuse test IP to create test programs quickly. Developing tests for enormously complex designs without using existing IP is simply not feasible. Any time-to-market advantage gained by adopting design reuse will rapidly dissipate in back-end test development. Consequently, engineers must actively manage the test IP just as carefully as the design IP.

The development of test IP and its reuse in a complex system-on-a-chip (SOC) design pose substantial challenges. The IP provider faces part of that challenge because test IP for a legacy core is likely to exist in the form of a tester-specific program. Although new test vectors could, in theory, be derived from the original design test bench, the program already represents a complete, verified collection of test IP. All that test engineers need are tools that translate the tester-specific test IP into a generic form, such as the Standard Test Interface Language (STIL-P1450). As new cores are developed, their test IP too should be translated into STIL.

Another challenge is that IC technology is a moving target. For example, a core and its test vectors might have been designed for a 0.5-µm CMOS technology, whereas a new system on a chip uses a 0.35-µm process. Just as new design libraries must reflect any new silicon process, test IP also needs timing adjustments that take into account the faster speed of the new process. The test engineers must then verify the modified test IP, either by building test parts for the core under the new process or, perhaps more practically, by using virtual test techniques to simulate and verify the new test IP timing.

Assuming that each core does include verified test IP, the engineers must determine how to reuse it in the system on a chip. A core might employ a variety of different test architectures. For example, one core might use BIST, another scan, and a third functional test. To complicate the situation, one or more cores may be embedded in the system on a chip, requiring a test bus or other access mechanism to enable each core to be tested. Furthermore, the interconnect between cores must be tested, and the test IP must be mapped to a specific tester.

Taking the test access requirements of each core into account, test engineers must synthesize a structure for the system on a chip to isolate and test each core and test the core interconnect. Commercial tools that perform those tasks are beginning to appear, along with associated tools that restructure each core's test patterns to allow access through the test accessibility structure.

Finally, after translation of the SOC test vectors into the target ATE format, new virtual test tools must verify again that each core's test IP was correctly captured and that the test patterns were correctly reformatted to fit the access architecture. The complexity of SOC testing makes that final verification step particularly important.

Concurrent design and test development and debugging is critical, for test development today is typically not concurrent with design. In many cases, the bulk of test development and debugging occurs after receipt of first silicon. In that case, mixed-signal devices--taking the most test development time--can delay time to market an additional 6 to 12 months. Even for digital devices, test development can push the time to market back several weeks. Though today's designs are simpler, they typically require significant test IP debugging on the tester.

Systems on a chip are too complex to have their test IP debugging postponed until after first silicon. To develop tests for them, test development will have to proceed concurrently with design. Virtual test technology facilitates the verification of test IP prior to first silicon, thereby allowing test to proceed alongside design. By employing virtual test technology, engineers can improve design-to-test communication, speeding systems on a chip to market.

SOC test architecture synthesis, pattern assembly, and standardized test formats such as STIL--along with virtual test verification--will help resolve test IP issues. The solutions will promote higher-quality testing that's ready at first silicon and speeds SOC designs to market.

David Flaningam is general manager of Integrated Measurement Systems, Inc.'s Virtual Test Division in Beaverton, Ore. He has served as vice president of Asian operations of Genus, Inc., a wafer production equipment manufacturer, and was a cofounder of Test Systems Strategies, Inc.

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integrated system design  September 1998