system design

Programmable Device or Gate Array? The various alternatives for small- and medium-sized logic devices require the designer to weigh the alternatives among field- and mask-programmable chips. by Vince Hopkin

OEMs in a wide range of markets need digital logic to perform various functions. The requirements for logic circuitry vary across the dimensions of gate count, speed, and product life cycles. Time to market, performance, board area, and low start-up costs often mandate the use of custom logic. But once you've made that decision, how do you determine what technology and product to use or whether a combination of solutions makes sense? User-programmable logic options for gate counts between 1,000 and 250,000 gates include the programmable devices known as field-programmable gate arrays, laser-programmable gate arrays, and complex PLDs; one-time-programmable devices include mask-programmable gate arrays, more typically referred to as ASICs.

For designs of low to medium complexity, field-programmable devices frequently offer the quickest time to market. The ability to program a device on demand allows the user to debug software and hardware quickly and make changes to the design immediately with a hardware solution. Programmable devices have moved up the technology curve and now boast gate counts well above the half-million range, thus remaining an option for customers whose requirements for complexity have increased. The high-gate-count programmable devices are often costly (in the $300-to-$1,200 per-unit range), however, so the designer trying to determine which programmable product to use faces a clear volume versus price trade-off.

Programmable devices vary with differences in granularity and architecture (see Table 1). Some are RAM-based and therefore volatile--they lose their data if they lose power. Some are nonvolatile, s0 they keep their programmed data even if powered down. Those devices generally rely on either antifuse or flash technology. The most popular programmable device architectures are the traditional product-term macrocell and the look-up table (LUT). Other devices--like the Actel and Quicklogic FPGAs--use various proprietary architectures.

The original fuse-based PAL used the product-term macrocell architecture over 20 years ago. The devices have grown in size and complexity; today, CPLDs incorporate arrays of PALs. The advances result from higher silicon densities and package technology improvements with ever-increasing package I/O pin counts.

The fundamental CPLD architecture consists of a plane of AND-OR logic driving a flip-flop, which in turn drives an I/O cell. The combination of the flip-flop and I/O cell is called the macrocell. CPLDs are generally measured by how many macrocells they contain. Compared with FPGA architectures, macrocell-based architectures require packages with high pin counts but support relatively few gates. They offer the best performance, however, particularly in propagation and clock-to-output delays. They are best suited for implementing finite state machine control logic and aren't particularly well suited for arithmetic processing circuits.

The popular FPGA LUT architecture consists of a function generator typically constructed out of a 16*1-bit RAM. The 4-bit input selects data in one of the 16 entries in the table. That method can easily produce any function out of the four inputs. The LUT output is then routed to a flip-flop to form a programmable logic cell. FPGA architectures are measured by how many logic cells they contain.

Unlike CPLDs, FPGA architectures don't include an I/O cell as part of the basic logic cell. Instead, the device contains special programmable I/O cells around its periphery. FPGAs offer higher gate counts and are generally more flexible than CPLDs, but their flexibility comes at the expense of lower performance. By incorporating special carry logic, FPGAs excel at implementing arithmetic processing circuits and are also suitable for implementing finite state machine control logic.

LPGAs, another type of programmable logic, are targeted at the quick-turnaround logic market because they offer higher densities than FPGAs, surpassing the 500,000-gate range. They're also programmed at the end of the wafer fabrication process, thus allowing a two- to three-day turn once a design has been laid out and validated. In terms of turnaround time, LPGAs are similar to fine-granularity gate arrays that are based on a sea-of-gates architecture. LPGAs and gate arrays differ significantly in unit price, density, performance, and prototype lead times. The differences stem from how and when programming takes place. Since LPGAs are programmed after the wafers are processed, turnaround time is quicker because base wafers are staged and then programmed, packaged, and tested in three days. Gate arrays, programmed at the metal process steps in fabrication, take longer to process but are customized more for density and performance.

The logical choice

Granularity is an issue with all programmable architectures. Suppose you need only one inverter driving a flip-flop. A CPLD consumes one macrocell and one I/O pin; an FPGA uses one programmable logic cell and no I/O pins. Conversely, if you need an eight-input AND gate to drive the flip-flop, the CPLD can fit the logic in one cell and I/O pin, whereas the FPGA might require three programmable logic cells. The CPLD is coarse-grained; FPGAs, on the other hand, offer various degrees of finer granularity. The effects of granularity depend heavily on the design; but from a device utilization perspective, finer is better.

The choice of a programmable device also depends on the types of memory supported. On-chip memory has become increasingly popular because many digital applications require FIFOs and other RAM structures. CPLDs don't support RAM; FPGA architectures feature RAM either in very small blocks using LUT memories such as the Xilinx 16x1 LUT, or in larger dedicated blocks--such as the Altera EAB memories--embedded into the FPGA array. Depending on your application's memory requirement, one programmable device family may be significantly better than another.

Gate arrays are appropriate for moderate- to high-volume applications that require moderate to high complexity. Gate counts range from 5,000 to 1 million, and clock frequencies can exceed 250 MHz. Since gate arrays are programmed at the wafer level, they're very cost-effective at reasonable production volumes. They also offer a wide range of memory solutions, including high-density compiled RAM, embedded RAM, and ROM.

Complexity is a primary consideration when deciding what approach to take. Gate counts can dictate whether a user should implement a design using a programmable device or a gate array. Though programmable devices have closed the performance gap somewhat, the basic trade-off remains the same: Gate arrays offer superior speed, power, and density, whereas programmable devices offer greater flexibility and much faster prototyping and production (see Table 2). The recent gains of programmable devices are tempered by differences in usable rather than actual gate counts; even in the hands of the best designers, programmable devices yield fewer usable gates than do gate arrays of equivalent size. But the beat goes on--Xilinx has recently started shipping its Virtex series FPGAs with a million gates, though a considerable amount of that is memory content, so that the gate total doesn't correlate well to ASIC gates.

The meaningful comparison of time to first prototype begins only at time zero, when simulation and layout are complete and the design is ready for programming. For user-programmable devices, volume influences the time-to-volume production, as the user must program one device at a time. The relationship between cost and volume drives many device decisions, as do total cycle time requirements.

The great flexibility programmable devices offer during the design process comes at a very high unit price that can far exceed gate arrays at certain volumes. Make sure to look at the various possibilities, since some programmables cost more than others--depending on complexity, speed, and package requirements.

LPGAs allow for very rapid prototyping, so they can be good quick-turnaround solutions for densities that exceed the capabilities of FPGAs and CPLDs. They have higher unit costs than gate arrays, so cost trade-offs should occur at any volume above 3,000 units a year.

A formula can help to determine which product is most cost-effective at a given volume. First, you must calculate the adjusted gate array unit price, A´:

A´ = A + (N/ T)

where A is the gate array unit price, N is the NRE for gate array, and T is the total volume of units produced over the product's life. Then use the adjusted gate array price in determining the total cost savings, CS:

CS = (A´ ­ F) x T

where F is the programmable device's unit price.

In one example, with A at $20, N at $15,000, T at 20,000 units, and F at $100, gate array production would yield a savings of $1.5 million over the life of the product. As volumes decrease, however, programmable devices become more cost-effective. Conversely, gate array unit prices increase heavily as volumes drop, since most gate array suppliers need to make a minimum amount of revenue to justify the engineering resources required for design services. Since the complexity of the logic drives cost for all of those solutions, break-even volume isn't constant. That's why doing a break-even analysis for any volume over 1,000 units makes sense.

Time to market is another consideration. One estimate states that for a new product, there will be a 5 percent drop in both unit price and product volume per month for every month's delay in release.

Another cost to factor in is the rate of gate array prototype failure: Only 90 percent of gate arrays work on the first pass, and only half of those actually make it into volume production without further spins. But if the customer has already verified the design with a programmable device, the hit rate for the succeeding gate array rises to 96 percent. For average gate counts of 10,000 to 20,000 (the estimated average for programmable logic designs), the cost of a gate array spin is approximately $50,000 (including engineering resource and tool costs). The analysis should include the added cost for the half of the designs that go from concept directly to gate array and the 4 percent of the designs that go from programmable device to gate array.

Determining what logic approach to use depends on many variables, including system needs, time-to-market requirements, and cost targets. A relative ranking of the technologies shows that each demonstrates areas of superiority and weakness (see Table 3). Ultimately, the choice depends on your priority for each criterion.

Many users will employ a combination of digital logic approaches. For example, an OEM can get to market quickly with a programmable device, then create an equivalent gate array during programmable device production, reaping the low-cost and high-performance benefits at the earliest possible date. Many OEMs favor such conversion from programmable devices to gate arrays; in addition, programmable device and gate array companies offer various conversion services, so choose carefully among them. Other OEMs like to market both field-programmable and gate array versions of a chip, serving the needs for reprogrammability as well as high performance and low cost.

The greater likelihood of producing usable silicon encourages OEMs to use programmable devices for initial prototyping, even when performance requirements mandate a gate array. Even though the device doesn't meet speed, designers are able to work on the initial software and hardware development with the slower part while the gate array remains under development.

When you're deciding on a programmable logic technology, don't forget to take the critical issues of software and human resources into account. Gate capacity, performance, granularity, and reprogrammability are important, but if it takes too long to design and program the device, then you lose a key benefit of the technology. The overall quality of the design software is a key issue. The design tools must be straightforward to use and supply accurate simulation models, predictable design results, and acceptable place-and-route and device-programming times. As always, time is money, and time wasted on design software issues can easily outweigh the benefits of small architectural or cost differences between competing devices.

Technical resources--or the lack of them--can also lead to the decision to use the multiple solution. For example, many OEMs employ experienced programmable logic designers but no ASIC designers. In that case, it may make sense to design in the programmable logic and then contract out the conversion to an gate array.

Programmable devices and gate arrays coexist because they offer different advantages, depending on the OEM's needs. Engineering and purchasing departments need to analyze each design based on performance, cost targets, volumes, product life cycle, and complexity. A thorough assessment of all of the factors often leads to an obviously correct solution.

Vince Hopkin is the director of translation ASICs at American Microsystems, Inc., in Pocatello, Idaho. He has held various manufacturing and marketing management positions.

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integrated system design  January 1999