asic/fpga

Making the ASIC/FPGA Decision FPGAs offer an ever more competitive technology as processes and time to market continue to shrink--even in the face of the ongoing move from schematic design to HDLs. by Rockland K. Awalt

If unlimited time were available and money no object, engineers could choose to implement a circuit in whatever medium suited their mood. In a world where time and money are always considerations, however, ASICs and programmable devices, such as FPGAs, each offer distinct advantages. Because time and money are limited resources, engineers must balance competing design constraints before they decide whether to implement a design in an ASIC or in an FPGA.

Several factors affect the decision to implement a design using an ASIC or an FPGA. For example, today's ASICs have a low cost-per-gate advantage as well as an inherent speed advantage; in contrast, FPGAs have been winning with their time-to-market, low nonrecurring engineering fees, and reprogrammable features. However, continuing process advances suggest that FPGAs will--and should--hold an increasing share of the market in the years to come.

Rolling the dice
ASICs generally cost less per gate today than FPGAs because they don't have the overhead associated with programmability. The cost-per-gate advantage that ASICs have enjoyed derives from their smaller die footprint: a smaller die = more dice per wafer = cheaper dice. Depending on who's making the prediction, the number of usable gates in question, and which of several other factors are taken into account, the overhead is somewhere between 12 and 50 to 1.

Figure 1	The shrinking FPGA
Current process geometries limit even the ASIC's gate count (a). As geometries--but not I/Os--continue to shrink, the FPGA will contain just as many usable gates as the smaller ASIC (b).

The cost of both ASICs and FPGAs has decreased over time, as Moore's Law predicted. However, cost also depends on other factors, such as learning curve issues, increased volume, gate count, and I/O pad count. Because ASICs are an older technology, most designers have long since factored in the learning curve. On the other hand, FPGAs have cut into ASICs' sales, decreasing their volume benefits. I/O pads cost the same for both ASICs and FPGAs, leaving gate count and Moore's law as the factors determining the future costs.

In other words, ASICs have already received much of the competitive benefit that they're going to receive from everything except gate count and Moore's Law--but Moore's Law applies equally to FPGAs (see Figure 1). After a few more generations, the law will render the cost of a gate irrelevant, because it has no effect on the input/output structures (see Figure 2). The chip still must interface with the outside world and continue to provide the appropriate input clamping and output drive. Thus once gates become small enough, the geometry of the bonding pads will limit die shrinkage and, ultimately, the size of an ASIC. When FPGAs can offer the same amount of usable circuitry within the same-size ring of bonding pads, they'll contain the same number of dice per wafer as the ASICs and gate arrays. At that point the FPGA vendors will be able to charge more per die because of the reprogrammability, but their cost per part will remain the same. The ASIC vendors, of course, will still be able to charge a premium for speed.

Figure 2	The costs converge
At some point in the not-too-distant future, the average cost per gate of the FPGA should equal that of the ASIC, overcoming one of the ASIC's primary advantages.

Today, though, if a product is going to be produced in great volume, the economies of scale favor the production of the design as an ASIC. An ASIC in volume costs $2 to $6 each, whereas an FPGA in volume costs $6 to $100 each. Given the price differential--and a long-lived, stable, high-volume product--it obviously makes more financial sense to do the design in an ASIC.

Notice, however, that the trend in the electronics industry is moving toward products that are increasingly of the short-design-cycle, upgrade-in-the-field, short-life cycle type, so there's an increasing demand for FPGA-style flexibility. And since such a trend implies lower volume, ASICs are becoming less often the correct solution.

Speed and time to market
Routing and gate delay determine the speed of a design. Since ASICs and FPGAs can support the same gate speed, ASICs gain their performance advantage primarily from their dedicated metal routing. All other things being equal, the soft routing of FPGAs makes them run about half as fast as ASICs.

A few engineers do the extra work necessary to improve the speed of an FPGA-based design, using such techniques as pipelining, linear feedback shift registers (LFSRs) for counters and dividers, and one-hot encoding for state machines. Of course, they could do the same for an ASIC-based design, but the fact is that most engineers don't want to do any of these things--for ASICs or for FPGAs. Designers pressed with time-to-market issues don't have the time to fine-tune their implementations. They just want to write some high-level VHDL or Verilog and get on with it.

Given enough optimization, though, FPGAs can serve to implement designs running at well above 150 MHz. For example, at Dynachip we've implemented a 155-MHz Sonet multiplexer/demultiplexer. In general, because most engineers are reluctant or unable to optimize their designs, a high-speed design today will end up in an ASIC--even if the volume is low and the product life short.

FPGAs have certainly won the time-to-market race. Working engineers know (because marketing tells them) that the time it takes to actually ship a product to their customers determines whether or not a product is successful. FPGAs have traditionally offered a faster, though sometimes more painful, route to sending a product to market quickly. They require design times roughly equal to those of ASICs, but once complete, they're essentially ready for market. An ASIC leaves a design house with NRE costs to pay and another 4 to 14 weeks of work moving the design into production. Note, however, that NRE costs have dropped considerably over the past few years--from about $250,000 down to $50,000--keeping ASICs competitive with FPGAs.

Reprogrammability
Reprogrammable devices such as FPGAs offer several advantages over ASICs and gate arrays. When the industry fought the battle over PROMs versus ROMs years ago, reprogrammability won, suggesting that FPGAs will overtake ASICs in the long term. Fundamentally, designers can survive more mistakes in an FPGA design because its reprogrammability gives them the chance to make course corrections along the way. The benefit, however, comes at a price--both economic and technical--that may be too high for a particular project, especially in today's highly competitive consumer markets.

If a design can benefit from time-multiplexing the hardware, then a RAM-based FPGA is the best choice. Often a design contains two or more functions that it never uses at the same time. By loading these functions into the FPGA one at a time, designers can greatly minimize the number of gates in the design and thus the size of the chip.

Most FPGAs don't allow partial reprogramming--requiring not only a large number of variant designs, but also the reprogramming of the entire FPGA with each of the design variations. Some allow a partial reprogramming of as little as one logic block at a time, which reduces the time to reprogram as well as the number of designs needed. The "hardware overlay" approach is slowly becoming more popular, but gate costs still make larger ASICs today's more common choice.

Of course, FPGAs also offer in-circuit reprogrammability--an important feature in the telecommunications and data communications markets, which change and add protocols all the time. As a result, designs must remain constantly updated to stay competitive and current with evolving standards. Given this scenario, an in-circuit-reprogrammable design is the best solution, making a RAM-based FPGA design the most sensible.

There's also a human element--stress--to the reprogrammability equation. ASICs aren't reprogrammable; the foundry casts their functionality in silicon. Making the final decision to commit a design to an ASIC can be extremely stressful for the entire design team. Once it makes the final decision, the team can't go back without incurring lots more NRE and lots more time. Erring at this stage, thus, is definitely a career-limiting move (CLM). FPGAs, on the other hand, offer engineers a greater comfort zone midway through the project, giving them the ability to go back and revise a design without paying the NRE and time penalties. Reprogrammability alone may well be responsible for much of the success of the FPGA marketplace in the last decade.

The ins and outs of FPGAs
Whereas ASICs have always supported every kind of I/O pad, FPGAs have offered the user only a few options. Such a limitation has been especially detrimental to FPGAs used with datacomm/telecom applications. Accommodating FPGAs has meant that the designer has to add more interface components on a board, thus consuming additional valuable real estate. All the same, datacomm/telecom applications make up a huge share of the FPGA market.

Simultaneous switching of outputs is also a limitation of most FPGAs. With today's higher-speed designs and wider data paths, the need to switch many output buffers simultaneously is important. All ASICs, being custom pieces of silicon, can accomplish this, but very few (perhaps only one) FPGAs have the ability to switch a large number of output buffers simultaneously. Fortunately, some FPGA manufacturers are beginning to offer some I/O relief, providing devices with LV-TTL, GTL, GTLP, AGTLP, PECL, and LVDS levels programmable on any or all I/O pins for most configurations.

ASICs allow a virtually unlimited number of clocks, whereas FPGAs can contain a limited number of clock trees. A design that requires a dozen clocks, supporting several loads each, demands an ASIC. FPGAs can handle up to 10 clocks, and now can offer analog phase-locked loops (PLLs) that were previously available only with ASICs.

Security issues should also be considered when choosing between ASICs and FPGAs. RAM-based FPGAs, of course, are a "volatile" technology--when the power goes off, the FPGA loses its configuration. In some cases that loss is a plus. For example, customers can restrict the programming of highly proprietary designs, such as an unmanned submarine detection buoy or an encrypt-decrypt engine. Using a battery to power the FPGA can safeguard the design from reverse engineering: if someone tries to tamper with the apparatus, the design completely evaporates.

A PC, however, must reinstall programming every time it boots. That's why there's no "instant on" with a PC. Although a nonvolatile device can provide the advantage of instant power, designers have modified most of the affected electronics to allow specifications that accommodate FPGA technology. For example, the popular PCI bus design now sports a longer startup delay to allow configuration of the FPGAs used in its design.

Design entry
In the past, the design entry method of choice for ASIC designers was a high-level design language; FPGA designers predominantly used schematic entry. Recently, because of a strong demand from a large part of the engineering community, FPGA software and hardware providers have been retooling to make their design process work more like the ASIC design flow. This retooling includes the ability to use an HDL, which unfortunately allows engineers to write inefficient designs.

As a result of the move to ASIC-like design flows, FPGA design is becoming increasingly abstract and automated, limiting designers' opportunities to intervene. Nonetheless, the trend toward automation is undeniable, partly because ASIC designers, as well as software engineers, have begun to use FPGAs; their preferred design entry method is textual, not schematic. Another reason for the move is that HDLs encourage portability, allowing a design to be moved from Altera to Xilinx or from Xilinx to a gate array. But let's just lump all the reasons together and call them "freedom." The freedom, however, takes a heavy toll in both area and speed. Though the demand for reasonably tidy, very high-speed designs remains strong, this new freedom produces increasingly less efficient designs in FPGAs.

This strong move away from schematic entry of designs, toward HDLs (VHDL and Verilog), has had an extremely negative impact on FPGAs that's still percolating down through the industry. Although FPGAs have been gaining ground on ASICs since the mid-'80s, this change to HDL design entry has all but stopped them dead in their tracks.

HDL compiler software inefficiency has a much greater negative impact on FPGAs than it does on ASICs, because FPGAs are inherently slower than ASICs. Granted, when compiled down to gates, HDL code can produce some fairly inefficient circuitry. But an abundance of performance in ASICs has always allowed for a certain amount of implementation inefficiency, enabling them to be more tolerant of the HDLs than FPGAs are.

Although HDL literacy and coding style (RTL is preferred for FPGA designs) has improved, it hasn't kept up with the rapid increase in the number of engineers attempting, for the first time, to use an HDL to design an FPGA. The percentage of new designs attempted suggests that the perceived FPGA performance is increasingly negative. Nonetheless, even though this design flow has left a lot of FPGA performance on the table over the past couple of years, the trend shows no sign of losing momentum.

Software issues are also influencing the shift from schematic design entry to HDL-based tools for FPGA designs. The members of a design team are going to select ASICs or FPGAs depending on their software tool experience. Designers come to a job with their own preferences and training; learning on the fly is risky.

Today, the design flows most commonly used includes an HDL, such as VHDL or Verilog, and a compiler-optimizer-mapper available from such companies as Exemplar, Synopsys, and Synplicity. These tools are built on a foundation that was originally developed for ASIC designers and are still much better suited to designing ASICs than they are for designing logic targeted to FPGAs. Hopefully, the tools will improve their performance on FPGAs as more designers employ them. In any case, FPGAs and HDLs are both here to stay.

Rocky Awalt is director of Dynachip Corp.'s Garden Valley Design Center in Sunnyvale, Calif. Having 35 years' experience in the industry, he has founded a number of companies including Highgate Design, where he developed the one-hot state machine. He was previously a cofounder and chief technical officer of Thea and a cofounder of Echo Communications.

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