Changing SOC Content Demands Codesign and Careful IP Integration

Codesign and careful integration of IP blocks are just two components of a methodology that will lead the way to a brighter future for system-on-a-chip design.

by Serge Leef

The nearly boundless transistor capacity available for advanced ICs is enabling an electronic system design revolution, one that will improve the accessibility and productivity of system-on-a-chip (SOC) design. Today, SOC development rests almost exclusively in the hands of large companies with abundant engineering resources and very deep pockets. We can largely attribute such exclusivity to the fact that traditional design practices, along with the tools and intellectual property (IP) that make up these advanced ICs, are ill suited for the task today. Early adopters of SOC methodology must therefore piece together a tool flow and throw a lot of manpower and money--some say in excess of $15 million per design--at the problem.

The explosion of activity in the telecommunications marketplace is fomenting the revolution that will bring this technology to a broader spectrum of users. The early SOC adopters today are primarily large telecommunications companies, but recent developments are setting the stage for more widespread use. The emergence of multicore system-level integration (SLI) platform chips and the increasing standardization of peripheral interconnect and telephony protocols enable critical design efficiencies and standardized architectures. These efficiencies represent a critical element in the proliferation of wireless and portable electronic systems--and in the use of SOCs to realize those systems.

Despite their importance in streamlining the SOC process, however, SLI platforms aren't sufficient to solve the SOC design problem. The overall SOC design methodology must evolve from the traditional content-creation-based flow to a composition-based approach to become more practical. Key components of SOC-oriented design are more in-depth system-level design and analysis, concurrent hardware/software design and verification using common tools, a verification environment that links a logic simulator with more productive tools such as hardware/software coverification engines, and the use of consulting services to augment today's SOC infrastructure.

Tough challenges

Though all of the hoopla today suggests otherwise, the concept of the SOC is nothing new. Since the 1970s, silicon and design automation technology has facilitated the integration of more and more functionality onto a single piece of silicon. With each advancement in silicon technology and the attendant increase in the number of transistors available on a single die, new design challenges emerge. The available transistors now exceed those required for most complete electronic systems, but accessing this near limitless capacity poses significant problems.

The most advanced ICs today are distinctively different from their predecessors. Integration of pre-existing content (IP) such as microprocessors, DSPs, memories, and other functions now constitute an essential component in design success. With on-chip programmable elements, embedded software (ES) design becomes an element in the design process. The combination of large complex IP blocks and embedded software, along with soaring transistor counts, taxes the capabilities of the traditional content-creation-centric design methodology--particularly verification tasks, which currently can consume as much as 60 to 80 percent of the design resources.

Figure 1 - SOC composition
SOC design represents a design composition problem much more than a design creation problem. Thus we are witnessing the evolution of IC design methodology from the content-centric flows of HDL- and schematic-based design to composition-centered block- or IP-based design.

The dependency upon pre-existing IP blocks to realize system functionality is a new wrinkle that poses tough problems for the SOC designer. Ideally, off-the-shelf blocks should greatly improve designer productivity, but few IP functions are reuse-ready. Many functions were originally designed for a specific application with little regard for use in external circuits. SOC designers wishing to utilize such functions must expend resources to modify IP to meet functional or integration requirements. Such modification precipitates design delays, complicates verification, and can ultimately defeat IP's theoretical productivity advantage.

Single-system implementations typically include one or more processors on board, a factor that complicates the SOC design problem further. The vast capabilities and the high performance of processors make them exceedingly complex entities to model and verify within a system. The addition of multiple processors--often the case in today's systems--amplifies this complexity. Traditional gate-level and RTL-based verification are among the tasks that languish under the burden of exercising a processor or processors in the context of a complete silicon system.

Along with embedded processors comes a companion SOC component--embedded software--presenting a new and awkward addition to the design flow. In the absence of silicon-oriented embedded software solutions, many have looked to board-based embedded SW and development tools for their SOC solution. Unfortunately, board-based solutions are woefully lacking for the purposes of silicon system development. Prototype-dependent debugging is arguably the most problematic aspect of the board-based approach. Waiting until hardware is available to check out software is unthinkable in the IC design world--respinning a design with software problems is not only prohibitively costly, but also very time consuming. Tools that enable concurrent hardware and software development address this problem and can improve design verification. However, these tools require changes in methodology as well as setup time and expertise.

The conventional functional verification methodology poses real problems when applied to advanced system chips. Dramatic increases in gate counts, complex blocks, multiple sources of content, and thus multiple simulation models bog down traditional simulation methods. Designers, either unaware or untrusting of more productive early-design simulation capabilities, still rely very heavily on tedious RTL and gate-level simulation to shake out most of their design problems. In large systems on silicon that contain complex processors and other components on board, analysis and optimization through this type of simulation can protract design schedules beyond reason, consuming 60 to 80 percent of the design schedule. Problems encountered at this stage can require painful and very time-consuming iterations through the design process. Though some early-design simulation capabilities--such as behavioral C-based or HDL-based simulation--can improve the initial design and reduce the likelihood of iterations in the back end, solutions for speeding back-end verification are evolving at a relatively slow pace.

Composing a methodology

SOC design is becoming much more a matter of design composition than of design creation (see Figure 1). Historically, HDL- and schematic-entry-based design flows have centered on the creation of new logic to implement the necessary functionality. Increasingly, ICs consist of a collection of IP blocks (microprocessors, DSPs, and other preexisting functions), memories, and moderate amounts of glue logic. For these circuits, devising how and what blocks to utilize, how to divide functionality between hardware and software, and how to interconnect and verify the system are the primary foci. A composition- or reuse-based methodology acknowledges this shift in focus and better addresses SOC designers' needs.

Four key factors distinguish an SOC design methodology (see Figure 2) from its content-centered predecessor. The first is a more demanding system-level design phase in which software developers and system architects consider in great depth IP block analysis, selection and interfaces in the design planning process. The second is SOC-centered embedded software design. Third is a multitiered verification methodology that takes full advantage of early-design simulation techniques, enables concurrent hardware/software verification, and minimizes the designer's dependence upon late-design verification for analysis and debug. Finally, since IP, EDA tools, and models today are still evolving to support the SOC design style, consulting services that serve to bridge gaps in tool and design expertise or infrastructure are often an important element in a block-based methodology.

Complex embedded system development begins with a system design phase. During this phase the development team analyzes requirements, studies legacy considerations, explores architectural alternatives, and ultimately partitions functionality between hardware and software implementations. At this stage the team determines such architectural issues as the choice of buses that facilitate communication within the chip, architectural platforms, and test/debug architecture (such as JTAG). In addition, IP selection takes place during system design.

Today, this complex and lengthy process produces a set of specifications. One of the specifications becomes the guiding document for development of the software. The other specification defines what the hardware team needs to implement. Today, the system design phase is executed by a group of experienced system architects, software developers, and hardware designers. Though tools that support architectural-level trade-off analysis are emerging, the system design process remains largely ad-hoc today, determined mostly by experience, intuition, and legacy considerations.

In modern design environments where numerous system components are either composed of or derived from pre-existing IP blocks, different and very significant considerations come into play during the system design phase. The architectural team must consider a wide assortment of tradeoffs associated with using a particular IP block or a combination of IP blocks in the context of the specific system that is being designed. In order to support this type of trade-off analysis, the IP blocks must be packaged in a way that facilitates their usage in the context of architectural exploration. The IP blocks need precharacterization to the point where the architectural team can assess the relative merit of the blocks with respect to broad goals defined for the entire system. The design goals can include a combination of performance, size, cost, and power dissipation metrics. In addition to form and fit issues, teams must also assess the quality, ease of integration, and reusability of IP blocks during the system design phase. Designers must consider such IP infrastructure factors as design for reuse and adherence to standards, a committed roadmap for future viability, ease of use, efficiency of contractual negotiations, and the support of accountable partners.

Figure 2 - A composition-based design methodology
A composition-based SOC methodology emphasizes an in-depth system-level design phase, and a cohesive verification process that ties together advanced simulation techniques for the various components of the design.

Another important consideration in IP selection is a particular block's suitability as delivered. Today, designers most often change the IP after acquisition. Modifying all of the various views and models that support the design process requires a tremendous amount of effort. This process introduces not only delay, but also risk, into the design process, and makes support by the IP vendor problematic. While some modification may prove unavoidable, designers are better served by wasting a tiny bit of silicon or functionality than by modifying a block. In general, it's best to select an IP block that requires no modification prior to integration, even if it means selecting a block that contains more features than required or compromising on non-critical features to use a simpler block without modification.

An embedded software development plan provides a dimension to the system design phase unique to systems with programmable elements. Off-the-shelf embedded software and debugging tools today predominantly target board-based implementation with little regard for the unique requirements of silicon systems. The memory configuration warrants particular consideration in deciding whether to develop or purchase embedded software. If the system contains embedded memory, traditional memory-hungry embedded software solutions will probably prove inadequate, requiring embedded software development.

SOC-centered implementation

The development methodology for systems with programmable elements requires embedded software development, but in the SOC domain this software development can occur only in the context of, and concurrently with, hardware development. An SOC-oriented ES development tool chain makes early-stage software design and validation possible, supports both hardware and software developers in a common environment, and accommodates multiple processors on chip. It's important that SOC software design and debugging tools--specifically functional verification, and prototyping environments such as emulators and JTAG-based hardware prototypes--plug into the hardware design environment at key points in the flow. Synchronized debugging of multiple cores poses a knotty problem, but nonetheless represents a key element in successful SOC design. Sophisticated tools that can handle the unique needs of the SOC designer stand within reach today, though they are highly specialized. Until platforms with standardized sets of processors in an application-specific architectural context become more commonplace, accessing these capabilities will require up-front development efforts in addition to significant expenditure on the tools themselves.

SOC verification arguably presents the greatest challenge to the designer, but available tools and methods can incrementally help to improve productivity. The designer remains constrained to traditional time-consuming and tedious logic simulation methods for detailed full-chip verification, so the key to improving productivity lies in reducing the amount of analysis, debugging, and optimization that takes place at this stage. The SOC designer must rely more heavily upon early design verification methods such as C-level or behavioral-level simulation and hardware/software coverification tools to shake out and optimize the design prior to detailed gate-level verification. At the core of the verification process must stand a proven simulation environment that supports simulation at all levels of the design flow.

Leveraging early-stage simulation involves examining the composition of the design and employing the best available methods for its various components. Processor functions demand rapid concurrent hardware and software verification that can be readily coupled and decoupled from the logic simulation environment. Likewise, instruction-set simulators and physical prototyping environments can move debugging along at a more rapid pace, then periodically resynchronize with the simulation environment. For SOC design, a common coverification environment for both hardware and software engineers facilitates more productive interaction as well as a more optimized implementation.

In addition to the processor components, faster verification is now possible for large IP blocks, memories, and custom logic. Abstract representations of large IP blocks--such as C or behavioral models--can also help to speed simulation. The C or behavioral modeling environment exercises these functions much more quickly than the traditional logic simulator, and then hook back into the simulation platform with interface information needed for system-level simulation. Similarly, memory blocks can be abstracted to more efficient representations. Finally, today's tools may be exercised to automatically generate intelligent test benches for glue logic and other custom elements.

Since the tools and components of an optimal SOC design flow are still evolving, consulting services that serve to bridge the gaps where tool and design expertise or infrastructure are lacking often comprise an important element in a block-based methodology. Having the right SOC infrastructure is just as important as having all the right tools, and consulting services can aid in the difficult task of pulling together the tools and methodologies for the specific SOC problem at hand. Utilizing outside expertise reduces design risk and helps establish SOC infrastructure for future product development.
External consulting experts can help with design tasks spanning platform development, IP assessment and tool integration, model generation, as well as software development, customization, and functional verification.

Despite the significant advances in SOC technology, the immaturity, cost, and uncertainty associated with SOC design is enough to keep many designers in a "wait and see" mode today. Many designers aren't feeling the pressure to design high-content chips, so the "make versus buy" proposition for design content can easily sway to the "make" side in light of the uncertainties associated with using external IP. The lack of viable SLI platforms makes SOC design a highly customized and expensive process that discourages many design teams. The partial EDA solutions now emerging are costly and require significant retraining. The dependence upon services to glue the methodology together can be uncomfortable to engineers who prefer more autonomy and control of their design process. The designer's reticence to embrace SOC design is unlikely to change until the cost, risk, and complexity of SOC tools, IP, and services abate, or until the competitive pressures in the marketplace dictate single-chip solutions.

In general, designers aspiring to take advantage of SOC design today must shift their focus to the early design stages and keep apprised of developments in the rapidly-changing tool and IP arenas. Application-specific SLI platforms that greatly reduce the need for tool and content specialization have only begun to emerge, and will go a long way toward streamlining the SOC design process. As efforts such as those of VSIA and EDA industry leaders improve the reusability of IP, adjustment to the new composition-based paradigm will become easier and less risky. System-level design tools and models aren't yet forthcoming, but would go a long way toward improving the efficiency of composition-based design. For example, high-level IP models that support architectural-level cost, function, performance, and power assessment would aid decision-making, reduce design risk, and improve productivity throughout the design process. The wish list is indeed a long one, but fortunately is receiving ample attention from industry players. The era of composition-based design has begun, and as it progresses it will create exciting possibilities for designers seeking to leverage the best that silicon technology has to offer.

Serge Leef is director of engineering at Mentor Graphics Corp's Codesign business unit in Portland, Ore.

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