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EDA Standards for the Millennium The increasing complexity of EDA tools and work flows calls for someone to create order out of the chaos created by proprietary interfaces. Industry groups are responding with a host of new EDA standards. by Steven E. Schulz

"Standards stifle innovation." "Committees produce too little, too late." Tried and true axioms? Perhaps--yet more EDA standards are in development now than at any other point in the history of the industry. Clearly, there must be more to the story.

The design landscape is growing more diverse, featuring interfaces that are simultaneously becoming more numerous but also more complex. Management has taken a more active and supportive role in directing resources for standards, recognizing that they need interoperability across those interfaces just to do business. System-level integration (SLI) now demands greater design productivity and design reuse, implying a shift to higher levels of abstraction. The industry requires new standards to facilitate interoperability at these higher abstraction levels and to reduce manual effort at lower levels.

As a result of the unprecedented standard-setting activity, users could see substantially enhanced design capability within the next few years (see the figure). Some efforts require the adoption of new methodologies to derive the full benefit promised, whereas others can immediately deliver enhancements within current methodologies. The advent of process technologies smaller than .25 µm has raised new hurdles to block the design process, providing an incentive for designers to accept change. A quick analysis of standards in most other fields (computers or wireless phones, for example) indicates that some standards can facilitate new industrywide capabilities not otherwise possible--a phenomenon that runs in stark contrast to traditional criticisms that standards represent yesterday's technology.

Interoperability of IP, tools, and libraries has become a global issue in the era of design reuse and SLI. Few EDA standards are developed today without worldwide participation prior to official standardization. The Virtual Socket Interface Alliance (VSIA) in Los Gatos, Calif., for example, has helped raise the awareness not just of how critical standards are in accomplishing new strategic business objectives, but of how difficult it can be to reach consensus in a global industry.

The three classes of EDA standards--defined according to their interface--include (1) user-to-tool (design languages), (2) tool-to-tool (such as EDIF), and (3) tool-to-physical (such as ASIC libraries). As automation advances, some user formats evolve into tool formats. In any case, the development of EDA standards over the next several years promises, at the very least, to make some sense out of the current chaos (see the table).

Revising the familiar
VHDL and Verilog are undoubtedly the most familiar EDA standards. Both enjoy tremendous success, providing the foundation of today's HDL-driven design methodology. Their momentum continues to grow with the help of supporting standards that serve to extend--or further restrict--both languages.

VHDL'99 is essentially a minor update of VHDL '93. VHDL International (VI) in Boulder, Colo., expects the revision to replace both prior revisions in all EDA tools. The primary benefits of VHDL '99 include greater design portability (default configuration binding rules, for example), a definitive implementation for shared variables, and a new VHDL PLI (VHPI). The language now implements shared (global) variables using protected types, with which the user may define any access methods. Synchronization across multiple VHDL processes--even when simulated on multiprocessor platforms--is handled automatically. VHPI will also provide any application with broad access and control over postelaborated design and simulation data. Both static and dynamic information is accessible, using either immediate or scheduled updates to design objects.

Verilog, first standardized in 1995, faces an IEEE vote on a new revision this year. Significant enhancements include a "generate" statement to automatically instantiate design objects (similar to VHDL), multidimensional arrays, bit-wise selection within arrays for test bench development, and improved file I/O (including binary write capability). Many hope this revision will also break the traditional dependence on Verilog-XL simulation behavior as the implicit language reference.

To match the digital Verilog standard, Open Verilog International (OVI) in Los Gatos has drafted an analog/mixed-signal counterpart known as Verilog-AMS, which will extend digital Verilog to support analog behavior across the time domain. The standard allows designers to describe conservative systems (supporting Kirchoff's laws) and signal-flow systems as equations, and mixed together along with digital functions. Verilog-AMS--fully backward compatible with IEEE 1364--supports a complete set of mathematical functions and operators, including the modeling of white, flicker, and frequency-dependent noise. LaPlace and Z-domain filters are included. An OVI ballot should decide the issue this year, hopefully clearing the way for IEEE standardization in 2000.

VHDL's modular and extensible architecture enables many enhancements--particularly those focused on systemwide modeling and higher abstraction--to appear as complementary standards that work together. VHDL-AMS, one important complementary standard, extends VHDL semantics for analog and mixed-signal modeling. It features robust top-down behavioral modeling for a variety of continuous systems, based on the theory of differential algebraic equations. Using such a mathematical foundation, the standard describes continuous-time systems independently of the algorithm used for solving them, allowing for various speed-accuracy tradeoffs with different solvers. VHDL-AMS models don't depend on time steps taken by the analog solver, nor do they require a closed-form expression. The standard also supports time and frequency domain simulation, as user-specified tolerance groups further ensure portability and fidelity. Because 1076.1 has been almost ready for some time, a number of tools, utilities, and models exist in advance of the final IEEE approval.

The Vital '99 standard for ASIC sign-off simulation libraries continues with major enhancements that are particularly suitable for high-performance SLI ASIC designs. Vital '99 now directly models multisource interconnect delays within an accelerated VHDL environment for greater timing accuracy, and it also integrates negative timing checks. The standard also offers a powerful new memory modeling capability that permits interoperable models of embedded memories to leverage timing-accurate and accelerated verification.

Figure	Design flow benefits from emerging EDA standards
The latest crop of EDA standards should offer substantial benefits to nearly every electronic designer. Timely adoption remains the greatest barrier to success.

Some important EDA standards

The Standard Delay Format (SDF) is a critical file format used universally to link tools for timing closure in the design loop. OVI approved SDF version 3.0 three years ago, but the last revision adopted by industry was 2.1. Though the IEEE 1497 committee is presently inactive, vendor adoption of SDF 3.0 could significantly reduce excessively large SDF file sizes through indexed label identifiers, while simplifying Vital modeling.

Adopting the proprietary format
Standards can take many paths. Besides in an open development process, other formats begin in proprietary forms that flourish in design flows. Some de facto standards are later contributed for continued industry-driven growth through standards bodies. Other proprietary formats diminish when an open effort duplicates its functionality without restrictions on use.

Though existing formats offer greater comfort, they can also create conflict. The Synopsys .lib format for describing synthesizable cell attributes and functions has become ubiquitous among ASIC suppliers (and EDA suppliers). Last year, Synopsys initiated a program, Tap-In, to license its .lib and Stamp library file formats (known as Liberty), and this year added Synopsys Design Constraints (SDC) to its licensed technologies. Last June, Cadence Design Systems, Inc. (San Jose) announced that it would open its popular LEF/DEF physical library and design formats, which have become pivotal as physical floorplanning becomes more tightly integrated with other technologies, such as synthesis. To deal with the multiple variations of the DEF file format, Cadence chose to resolve the differences using an application-programming interface (API) approach.

The implementation tactics taken for Liberty and LEF/DEF have proven to be quite controversial. Synopsys was initially criticized for refusing to place its library technology in the public domain, which led to the creation of a competing format, the Advanced Library Format (ALF). As ALF gained momentum several years later through its inclusion with the Delay Calculation Language (DCL) in a new library format, the Open Library API (OLA) standard, Synopsys then announced the Liberty program. Cadence had similarly refused to place LEF/DEF in the public domain. As Cadence revealed the details of its plans to release object code only for the API interface, Synopsys led an industry charge claiming, ironically, that Cadence hadn't been open and fair. The discord continues with the Synopsys-led formation of a new standards committee to create a competing format for LEF--OPEF (Open Physical Exchange Format). Undoubtedly, 1999 and 2000 will write more chapters to this unfinished tale.

Taming the current methodologies
Whereas some standards under development aim to make today's methodologies work better, others are attempting to support entirely new capabilities by embracing emerging design methodologies.

Prior to the mid-'90s, designers wrote HDL models first for simulation, then for synthesis. The synthesis revolution, however, turned the restricted synthesis subset into the reference for verification as well. Unfortunately, the interpretation of the HDLs for synthesizing hardware wasn't interoperable across tools, complicating attempts to verify functionality across RTL and gate-level code. Furthermore, designers currently ignore robust HDL modeling features because the current languages only vaguely handle the semantics of hardware design intent. In response, VI and OVI have partnered to create a pair of standards for synthesizable subsets in both VHDL and Verilog, based closely on today's de facto standard. The VHDL Level 1 subset is now IEEE 1076.6, and the Verilog subset is nearing completion. A second level for VHDL, now in the works, will unleash much greater descriptive power in modeling for synthesis. Anticipated features include support for array, composite, and record types, functions, generates, and multiple architectures.

Semiconductor suppliers have long struggled with the problem of making data sheet information rapidly available to OEM companies, information brokers, and the mass market of designers. Furthermore, getting that data into EDA tools has been costly and problematic. The Electronic Component Information Exchange (ECIX) project solves these problems through several complementary standards, including a component information standard derived from Pinnacles, (PCIS), a component dictionary standard (CIDS), a timing diagram markup language (TDML), and SGML. ECIX will support both PCB and SLI ASIC design, allowing components to be instantiated as cores.

The Electronic Design Automation Consortium (EDAC; San Jose) has initiated its own interoperability project, dubbed Spine '99. Based entirely on current version file formats and tools, Spine '99 is constrained to file-level interoperability between Synopsys' Design Compiler and Cadence's Silicon Ensemble. It includes verification of the flow, which could result in code patches to the applications if required. EDAC members hope that once they've clearly documented the flow, other EDA vendors can connect to the flow in a similar manner. Certainly, EDAC has yet to resolve several essential aspects of Spine '99, such as how (and where) to perform verification testing and what its commitment to continue with future versions of tools and file formats will be. Some users have criticized the effort as being too little, too late. However, EDAC emphasizes that this is the first time the EDA industry has taken responsibility for ensuring interoperability, and it hopes to build on a cooperative foundation. Yet the conflict over OPEF reveals that this cooperation is already under strain.

Wrestling with the new
An unprecedented number of electronics companies and EDA suppliers have joined forces worldwide to promote several fundamental design methodologies that come with prerequisites for new areas of interoperability. These emerging methodologies, summarized below, must adhere to the standards that will allow them to function within practical design flows.

Typically, standards are implemented using ASCII files. However, for high-bandwidth communications between tools, APIs are slowly becoming the preferred approach for tightly coupled design steps. The shift to APIs becomes especially critical to better manage concurrent design trade-offs and incremental design changes.

One example is the new OLA standard, which builds upon two other standards--ALF and the Delay and Power Calculation System (DPCS). DPCS, now approved as IEEE 1481, changes the paradigm for performing timing and power calculation across the design flow. Rather than fighting the futile battle against inconsistencies inherent in different delay or power algorithms, ASIC suppliers can now offer a single certified library that delivers consistent and accurate results for the most advanced silicon processes. Unlike traditional libraries that supply parameters only, compiled OLA libraries are dynamically linked executables that communicate with the application. Besides achieving consistency, the OLA standard can improve overall cycle time by eliminating long file read/write operations and enabling rapid re-analysis of what-if design changes. Furthermore, ASIC suppliers need not disclose their precision algorithms to competitors. The OLA draft standard includes additional API routines to communicate synthesis attributes and functionality, defined by ALF and embedded within DCL/DPCS tables. The IEEE 1481 standard also incorporates two closely related file formats (PDEF and SPEF; see "OVI: Putting EDA Standards into Practice").

The trend toward concurrent logical and physical design is perhaps best exemplified by the Sematech-sponsored project entitled Chip Hierarchical Design System, or CHDS. The CHDS standard is broad in scope, being a proper superset of DPCS. A large set of API-based interfaces makes possible a multivendor "plug and play" design system. The technical data interface standard--Chip Hierarchical Design System Technical Data (CHDSTD)--is a fundamentally new design flow architecture, consisting of a comprehensive information model and a set of application programming interfaces. Its aggressive goals will take years for full-scale adoption. However, most industry leaders today recognize that complex submicron chip design requires a more concurrent methodology, and that high-bandwidth data interfaces will ultimately require incremental, demand-driven socket interfaces between interacting tools and libraries.

The second major trend requiring a methodology shift is the move toward design and synthesis at higher levels of abstraction, notably those including both hardware and software. SLI ASICs must integrate a wide variety of multiple processors, memories, buses and protocols, software, and mixed-signal functionality--yet no format exists to design a system at this level and analyze performance trade-offs at the architectural level for partitioning and cosynthesis. The System-Level Design Language (SLDL), a worldwide standards-bound initiative to fill that void, is now under VI's sponsorship and supported by Darpa, ECSI, EIA-J, IEEE, and OVI. SLDL is being developed in two distinct phases: The first defines a systemwide constraint language (developed in cooperation with the RTL design constraints working group), whereas the second will add a semantic framework for integration of selected functional languages for partitioning and cosynthesis.

Ultimately, though we don't yet know which of these standards are destined to change the course of EDA, one thing is clear: Standards in general have the capacity to serve both vendors and users well, and the coming years will continue to witness more and more efforts to gain control over the explosion of EDA tools and work flows for the ultimate benefit of designers worldwide.

Contributing editor Steve Schulz is a senior member of the technical staff in Texas Instruments, Inc.'s Worldwide ASIC division in Dallas. He serves as the president of the board of directors of VHDL International and is executive sponsor of the System-Level Design Language initiative.

To voice an opinion on this or any Integrated System Design article, please email your message to jeff@isdmag.com.

integrated system design  June 1999