Alternatives to CMOS Processes Promise High Speeds--At a Price

Though CMOS processes have yet to reach their size or performance limits, alternative processes have already carved niche markets for themselves and appear poised to make some inroads into the mass markets.

by Tets Maniwa

As we continue to move down the path predicted by Moore's law, the rationale for choosing a particular process may change with the technology. In the near future, the technology of choice may no longer be CMOS, primarily because we are running into some fundamental limits in our ability to continue to scale performance in the latest generation processes.

The next generation of designs will sport clock frequencies in the GHz range, contain many millions of gates, and utilize complex power management schemes. We can assume that the EDA tools will evolve and acquire the capabilities to complete this class of design, albeit at a slower rate than the silicon processes. The big question: Can the standard CMOS meet the performance requirements?

CMOS has been and will remain the dominant technology in almost all applications, since it offers several important advantages. CMOS is an extremely mature, production-proven technology that includes very rich and powerful design resources. Its well established processes continue to mature. The powerful trust given CMOS by leading-edge digital memory and processor vendors has led to continuous improvement and scaling of CMOS processes.

New circuit topologies and design techniques are overcoming the physical limitations and characteristics of the process. In the past, CMOS worked well only for logic and memory. Now many analog functions in CMOS can outperform the equivalent in bipolar circuits. When device characteristics such as low DC gain limit performance, designers can address the limits by increasing the circuit complexity and establishing a higher gain-bandwidth product in the CMOS devices. In addition, system architectures are taking advantage of the increased performance available and have incorporated greater and greater amounts of digital rather than analog signal processing. At some point, however, CMOS will hit a wall that it can't scale, and technologies such as gallium-arsenide (GaAs), silicon-germanium (SiGe), and silicon on insulator (SOI) may rise out of the niche markets they now occupy.

CMOS limits

At the 1996 IEDM meeting, Gordon Moore, the founder and former CEO of Intel Corp. (Santa Clara, Calif.), revisited his original projections for devices on a chip from his original 1968 and 1975 presentations on the same topic. He noted that the changes in processes that enabled the tremendous increases in device count, die size, and circuit complexity are facing fundamental limits by the year 2010.

For the processes smaller than 0.35 µm, interconnect will limit performance. As the number and complexity of interconnect layers increase, the interconnect begins to dominate delays and power consumption, and will continue to be the primary factor in performance despite changes in metallurgy and dielectrics. Synthesis-based designs have an average fanout of 3.5 to 5, increasing not only the total amount of interconnect, but also the average length of that interconnect. The average length increases because designers can't locate all of those gates close enough together to optimize the interconnect lengths.

Another problem for all processes, not just CMOS, is lithography. The continued increase in functionality will require something other than continued scaling of device dimensions. As we move to and below the 100-nm dimensions, some fundamental issues require resolution. At some point, the thinner lines become too small to resolve the details of that feature. The costs for the research and development plus the very high expense for a new wafer fab will make the adoption of the very small processes more risky than even the current generation faces. The problems will only increase, because of the relatively short process life time and the rising costs of state-for-the-art wafer fabs--$2 billion each for the 0.2-µm generation and a whopping $4 billion for the 0.15-µm generation.

Table - Material Characteristics
Name	Symbol	Germanium	Silicon	Gallium
Bandgap energy at 300° K	Eg [eV]	0.66	1.12	1.424
Breakdown field	Ebr [V/cm]	10 5	3 x 10 5	4 x 10 5
Mobility at 300° K (electrons)	mn [cm2/V-s]	3900	1400	8800
Mobility at 300° K (holes)	mp [cm2/V-s]	1900	450	400
Relative dielectric constant	es/e0	16	11.9	13.1
Thermal conductivity at 300° K	c [W/cmK]	0.6	1.5	0.46

The atomic nature of matter will become more evident in future devices. Current processes produce devices with interlayer dimensions of a few tens of atoms, so the continued decrease in layer thickness isn't continuously extendible. Researchers are starting to address single-electron device issues, but the technology may not be ready by the time the silicon reaches other limits. Therefore, the advances in engineering that have propelled technology for the past 30 years are approaching fundamental limits, so we may not continue on the curve that doubles density and performance every year beyond the year 2010.

To overcome some of these limits, the industry is looking toward advances in the existing technologies and advances in other processes. The vast majority of research and investment is in the base CMOS processes. The big circuit and device conferences like IEDM (International Electron Devices Meeting) devote most of their coverage to complementary transistor devices on a silicon substrate. And no wonder--the basic CMOS technology warrants concern for several reasons.

CMOS devices face an operating speed ceiling, largely because of their capacitive nature. The main claim for such circuits is that in static operation, they use very little power. Yet power consumption in CMOS is a linear function of operating frequency and total (switched) capacitance (P = f * C * V2): as the operating frequencies and gate counts increase, so does the power. Together these two components are increasing much faster than voltage reductions can decrease the power, resulting in an overall demand for power. The Alpha microprocessor, running at 600 MHz, devotes a third of its operating power--about 16 W--to the clock tree.

Similarly, the device parasitics in CMOS restrict the devices at the upper operating frequencies. The ft or fmax of an nmos device is in the tens of GHz, while the pmos devices are slightly slower because of lower carrier mobility. However, transit times in the alternative processes are higher than in CMOS (see the table).

Scaling dimensions and voltages as the lateral device dimensions continue to shrink, designers must make corresponding changes to the vertical ones to maintain performance. The thinner oxides suffer voltage field breakdown problems if the supply voltage isn't scaled with the oxide thickness. Most semiconductors have field breakdown voltages in the 105-V-per-cm range. With a gate oxide thickness of 3000 Å, the electric field across the oxide with a 1-V signal applied from gate to drain is about 105 V/cm. Fortunately, in this instance supply droop and ground bounce are working in the designer's favor. The driving stage, because of internal resistance, can't achieve a full rail-to-rail swing, and the voltage across the rails is compressed by the IR drop on the supply and ground lines. These effects help to prevent immediate and catastrophic gate oxide failures. These lower supply voltages, however, are very bad for the analog, mixed-signal, and RF stages where the lower supply voltages increase noise susceptibility and decrease the signal dynamic range.

In addition, the process scaling causes some second-order device characteristics, such as subthreshold operation, to become more significant to the overall performance of the devices. The smaller processes increase the mismatch in CMOS devices, already relatively high, because the tolerances in the line widths and layer thickness are measured in absolute values and not in percentage variations. For example, if a lithographic process supports an absolute resolution of 10 nm, this resolution amounts to a 4 percent possible error in a 0.25-µm process, but a potentially catastropic 10 percent error in a 100 nm process.

Variations on a theme

The major disadvantages of CMOS technology relate more to the portions that aren't digital, but the digital circuits will have to face these issues in the future. The leading-edge processes are neither characterized nor tuned for analog circuit design. This lack of process characterization becomes more important as the digital circuits assume more analog characteristics.

In the past, analog designs were all bipolar. Now with improvements in devices and new design techniques, CMOS can work in analog circuits at supply voltages down to 3 V with 90 dB of dynamic range. The high-performance analog circuits will always need the voltage to perform. So, as the technology scales to the smaller dimensions, the core digital functions will operate at 1.5 V or less. The lower voltage enables higher speeds, as signal swings are smaller, but at the same time reduces the dynamic range for the circuit and system.

John Corey, general manager of the analog and memory core design group at Lucent Technology in Allentown, Penn., develops circuits for other Lucent business units. They focus on embedded memory and analog circuits. Other design groups do the standard cell and macro functions. Corey notes that "in general, the mixed signal cells are greater users of the nonstandard processes. Most circuits are in CMOS, with some in SiGe or BiCMOS, especially the RF and very high-performance analog functions."

The limitations of the standard CMOS process steer designers toward the easiest migration path. Some of the alternative processes like BiCMOS (mixed bipolar and CMOS) and SOI (silicon on insulator) use CMOS as a base and make changes to the supporting silicon and processes to achieve devices with different characteristics. In the cases of process variants, the changes to a process aren't new characteristics, but just some of the parameters that come with the underlying device structure. BiCMOS has always been available, but in the past, the complexity and cost of BiCMOS processes has limited their use. The bipolar devices were already available as parasitic elements, even though the inherent bipolar devices aren't optimized for any particular parameters.

BiCMOS processes provide an additional bipolar device that has served as the workhorse of analog design. The bipolar transistor can increase the speed, reduce the mismatch, and obtain better circuit characteristics when a design requires an exponential I-V relationship. In addition, the bipolar devices can operate at much higher voltages than the MOS devices, since the breakdown voltages are a function of diode junction breakdown based on relatively thick semiconductor junctions, and not an oxide field voltage. Now, the bipolar devices in BiCMOS address the very high-speed functions like CDMA and fast SONET.

BiCMOS offers the manifold advantages of CMOS density combined with enhanced capabilities for lower power and higher speeds. In digital parts such as DSPs, CMOS provides lower power, since the circuitry can be set up to gate off the clock sections that aren't in use at the time. RF, in contrast, is a full-time function, so the designs need to possess the lower power and noise figures of bipolar to work.

Variations, Volume 2

Silicon on insulator (SOI) also looks very similar to standard CMOS. Originally developed as silicon on sapphire (SOS), SOI isolates each device in a insulating oxide pocket and thereby reduces device-to-substrate parasitics as well as interdevice interactions. The process exhibits good high-temperature characteristics and high resistance to radiation effects, so it is especially useful for high reliability and space applications. These reductions in device parasitics improve the performance of individual devices, and enable much greater system performance.

The disadvantages of SOI are much higher wafer costs and more complex design requirements. The lack of a path to ground through the substrate can cause threshold shifts and other unusual charge accumulation behaviors. In addition, the need for a thick oxide pocket around and under each device moves the devices farther apart, lowering total circuit density.

Another silicon variant is relatively new. SiGe (silicon-germanium) is an unusual hybrid material for very high-speed bipolar transistors. SiGe is similar to BiCMOS since processing starts from a standard silicon wafer and mixes germanium in the base layer of the bipolar transistors to achieve higher cut-off frequencies in the transistors. The benefit of combining germanium in the base is that the hole mobility of germanium is about four times faster than silicon, leading to much faster devices. So far, in addition to the speed, the main values of the SiGe process are lower noise and device parameters that closely approximate the ideal.

The higher speeds of the silicon-germanium process may mirror the operating directions for CMOS. Because the base layer is developed as a multilayer sandwich of silicon and germanium, the layers are very thin, to minimize the lattice disruptions. This thin base region results in fairly low breakdown voltage, so the operating voltage can't be too much higher than that of the other circuitry.

Seshu Subbanna, manager of SiGe process technology development at IBM Corp. in Hopewell Junction, N.Y., says that the company "does analog cores in bipolar for a number of reasons. One is because the analog sections don't have to scale with the CMOS. Due to their structures, bipolar devices can operate at much higher voltages than the scaled CMOS, so the analog sections can operate at 3 or 4 volts or whatever, even while the digital sections are operating at 1.5 V. The front-end sections in analog are then transformed to digital signals for the CMOS digital sections to process."

Figure - Other III-V devices
Cross section schematic and SEM of InP HEMT from IEDM Conference 1998.

Different strokes

Because the majority of the alternative processes are geared toward the analog and mixed-signal functions, the simulation of such systems presents one large problem. The difficulty lies in finding reasonable tradeoffs in tools that provide speed and capacity for the circuits that are too large for today's tools. Dale Jadus, SiGe model and characterization manager at IBM in Essex Junction, Conn., notes that "the main challenge is the whole area of mixed-signal design. The challenge is to develop ways to simulate circuits that have mixed digital, analog, and RF sections. One part of the problem is that there are many different designers, techniques, and methodologies for mixed-signal design, so it is hard to supply a single tool that addresses all possible types. Even providing just the appropriate tools is hard."

Some processes, such as GaAs (gallium-arsenide) and other III-V processes (three-five, from the columns in the periodic table of elements with three or five electrons in the outer valence band) start from a different base material and try to end up with an active semiconductor that contains characteristics quite different from the original materials. Given today's atomic-level processing capabilities, device designers can specify junction profiles and therefore device characteristics in much more detail than is possible with naturally occurring materials. GaAs processes, recognized for their fast operation, are ticketed for high-speed systems--and for good reason. The speed-power product of GaAs is better than the equivalent in CMOS because the electron mobility is about 6 times faster in the GaAs than in silicon. Furthermore, GaAs is a high-resistivity substrate that yields better signal isolation than BiCMOS.

The GaAs processes suffer from several problems; most importantly, the processes are less mature than CMOS. The GaAs processes were originally developed for military and RF applications, so the manufacturing and design didn't need to resemble CMOS. GaAs processes are generally expensive and not easily accessible. In the past, GaAs has focused on smaller functions, emphasizing RF and other specialized functions. The GaAs vendors have used gold as the metal for contacts, and must employ air bridges for insulation. It has been difficult to achieve good yields, because the various functions produce smaller volumes than the mainline CMOS.

Tom Costas, director of operations at GHz Circuit Design, Inc. (Santa Clara, Calif.), notes that the frequency range determines the most applicable technology. For example, in a 0.25-µm TSMC process, the ft is about 27 GHz, so the maximum operating frequency is at most 2.7 GHz. If the design is meant to run at 20 GHz, the only process that can meet the requirements is GaAs. In some cases, cost is a factor. The company asks their customers about potential quantities and target costs. In one particular case, the user was spending about $100 for discrete components. Redesigning the circuits in GaAs drove the cost for the full IC-including the former discrete components--down to less than $25.

The main application for GaAs has been in RF and analog circuit design, influenced by the Schottky diode at the gate (see the sidebar). Since the diode is in a forward bias direction, an enhancement mode MESFET contains a gate-source voltage range of 0.1 V to 0.6 V.

Chris Gardner, vice president and general manager of the telecom division of Vitesse Semiconductor in Camarillo, Calif., observes that "the applicability of GaAs depends on the end application. For many high-speed applications, either CMOS or GaAs can perform the job, but GaAs gives better noise, jitter, and slew rate performance than CMOS. Currently their design flows are very similar to CMOS. In physical layout, they can port designs from CMOS to GaAs or vice versa with minimal difficulty. This ability to port designs is very unlike bipolar designs, which can't be migrated nor converted to CMOS easily."

The MESFETs

The Metal-Semiconductor-Field-Effect- Transistor (MESFET) consists of a conducting channel positioned between a source and drain contact region, as shown in the figure. The carrier flow from source to drain is controlled by a Schottky metal gate. The designer controls the channel by varying the depletion layer width underneath the metal contact, which modulates the thickness of the conducting channel and thereby the current. The principal advantage of the MESFET is the higher mobility of the carriers in the channel as compared to the MOSFET. Since the carriers located in the inversion layer of a MOSFET have a wave function that extends into the oxide, their mobility--also referred to as surface mobility--is less than half of the mobility of bulk material. As the depletion region separates the carriers from the surface their mobility nears that of bulk material. The higher mobility leads to a higher current, transconductance, and transit frequency of the device.

One other process--based on indium-phosphide (InP)--threatens to break speed barriers (see the figure). The three-terminal devices that include high-electron-mobility transistors (HEMTs) based on InP are already boasting speeds as high as 350 GHz, with 3 ps gate delays.

Something for nothing?

CMOS will continue to stay at least one processing generation ahead of GaAs because of the volume, resources, and money focused on CMOS development. The alternative processes are good for their niches but are unlikely to ever become as widely used in mainstream applications.

Bryan Lewis, principal semiconductor analyst at Dataquest (San Jose), says that in his personal opinion, GaAs, BiCMOS, and SiGe will stay niche. We are hearing more and more on the use of SiGe in communications but in the big picture it will remain in a niche. SOI, in contrast, shows some major potential and could account for as much as 40 to 50 percent of the semiconductor market in 5 years.

The alternative processes are addressing the performance issues, especially for the RF functions. Subbanna of IBM calls the design of anything in special processes a "custom development." They try to tell their customers about some of the fundamentals of RF design--such as RF shunts and substrate coupling--and provide their customers with the information as a part of the training in design that they give to all their customers. With some special design and layout techniques, they can achieve good isolation at operating frequencies of 2-10 GHz. As the related RF design grows, users need to obtain (and use) a different set of knowledge, skills, and experience to create successful designs.

Costas of GHz Circuit Design agrees and notes that the design processes are similar enough that they can use standard tools for their designs--in their case, Cadence tools for the design of the RF and mixed signal sections, and for layout. As important as the tools, however, they need to furnish the design deck with accurate models, design rules, and other documentation before working on the actual circuit implementation. If they lack prior experience with a foundry, they run test circuits in the first spin, to check the process parameters and performance. If they can't manage a first spin, they try to do a wafer run with special test structures to get a feel for the actual performance.

The ASIC market will continue to invest and support CMOS as the standard process of choice for the foreseeable future. The alternative processes will fill the needs of the design community for special-purpose applications such as analog, mixed-signal, and RF. As the manufacturers gain more experience in other processes, they help to extend the duration of Moore's law, and increase the performance and level of integration, while reducing the costs of the products.

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