Part of the answer lies in what we call "design plan synthesis," a combination of methodologies and automation that estimates design characteristics for use in the early stages of a design. Specifically, design plan synthesis provides the automatic creation and optimization of multiple design plan alternatives to meet target timing, power, and area objectives at the architectural, RTL, structural, and physical levels of a design. Tools automatically evaluate multiple design plan alternatives early in the design process, and provide continuous refinement of the design plans as designers develop the individual blocks. The tools also present more detailed timing and place-and-route information. In short, design plan synthesis not only streamlines the synthesis and verification of the design, but also saves designers from encountering some nasty surprises at the layout stage surprises that can add weeks and even months to the design schedule.

Gates versus blocks Today, advanced deep-submicron processes are yielding minimum feature sizes that approach 0.10 ým, clock speeds that approach 1 GHz, five or more metal layers, and transistor counts in the tens of millions per chip. In addition, competitive market pressures mean that IC designers working within these advanced technologies are developing complex ICs that may have a total life span of less than a year. Stretched, therefore, between increasing development demands on one hand and decreasing delivery schedules on the other, the traditional gate-level design methods can no longer offer successful development strategies. The combination of massive design sizes and the escalating impact of the resultant physical effects creates design demands that markedly exceed the capabilities of conventional gate-level tools.

The deep-submicron processes used to manufacture today's ICs have changed the nature of the fundamental design process in a number of ways. In the past, front-end logic designers had the luxury of simply ignoring certain physical considerations within the chip because the relative impact of those physical effects was negligible given that the cell library was pre-characterized. Designers wasted little effort worrying about timing, crosstalk, noise, ground bounce, and other issues pertaining to circuit performance and signal integrity. As long as they developed circuits that were functionally correct, design engineers had every reason to believe that the physical implementation of those circuits would map faithfully to the intended purpose. Now, however, interconnect delay overshadows gate delay; fringing capacitance presents a more significant design challenge than capacitance to ground. Clearly, the front-end designer can no longer afford to ignore the sometimes debilitating effects of physical implementation. More than at any time in the past, the IC designer must work meticulously, fully cognizant of all aspects of both logical and physical design.

For a complex IC design, the detailed netlist-driven results available from conventional gate-level tools arrive too late in the development process far too late to satisfy the designers' needs for information on the impact of a particular design approach on die area, power consumption, and overall chip performance. Designers have found themselves reaching the final layout stages only to discover problems that require them, regrettably, to redesign logic and to resynthesize gates to meet all the timing, power, and area requirements.

Given the size of today's designs, designers commonly find themselves waiting days for completion of lengthy synthesis, placement, and timing analysis runs and even then, forced to resort to additional iterations to deal with newly uncovered timing or area problems. For instance, on large designs comprising hundreds of thousands of gates, designers using traditional approaches currently find that they may need many place-and-route iterations to meet all the performance objectives. In some cases, designers have had to run twenty or more iterations of placement and routing to make the design work a situation that clearly threatens the semiconductor industry's ability to satisfy market demands in a timely and cost-effective fashion. In today's competitive marketplace, such delays can prove very damaging to the market position of the design company. Fortunately, block-based design methods can help designers incorporate physical knowledge early in the design and help designers to avoid costly design iterations.

Block-based design challenges

Just as design complexity outpaced schematic-based design entry in the 1980s, the demands of today's massive IC designs are driving the next phase in the evolution of design technology (see Figure 1). Flat, gate-level physical implementations are reaching the limits of productivity for high-speed or multimillion-gate designs in turn, driving the migration to a block-based, or divide-and-conquer, approach to physical design. This modular approach reduces the impact of incremental changes and helps to establish localized timing domains for each block, thus making timing convergence much more manageable and predictable. It also facilitates the team approach by allowing individual team members to work in parallel on different blocks.

Figure 1 - Design Complexity Evolution

New levels of design complexity are driving designers to explore and utilize block-based design methodologies.

Although block-based methods let designers tackle complex ICs as a collection of smaller, more manageable blocks, they levy a whole new set of demands as well. In particular, the current generation of block-level design tools suffers from a number of inadequacies that limit their usefulness.

Current design planners provide the ability to complement logic synthesis with a broad range of gate-level implementation services. These tools let IC designers partition gate-level netlists and conduct post-placement optimization as well as incremental resynthesis. Yet IC designers can't fully exploit the power of these design planners until a gate-level netlist is available. Even when utilizing design planners early in the design process, the engineer doesn't reap any tangible benefits until late in the process, during or even after logic synthesis has produced a gate-level netlist for each of the synthesizable blocks long after the chip architecture has been completed.

Because design planners thus offer little assistance until late in the design process, they can't provide the front-end logic designer with critical feedback on physical implementation characteristics. Quite often, the back-end physical designer becomes stymied by timing, area, and power requirements that the front-end logic designers could easily have met had they only known that serious problems would arise during physical implementation.

Finally, when it comes to planning pure block-based designs, the current generation of design planners offers the IC designer very little in the way of automation. The IC designer must still manually place, size, and shape blocks in order to make the best use of available top-level routing resources. While numerous feedback and analysis tools help the designer identify problems with wire congestion and poor port placement, they don't offer automatic capabilities to then help the designer quickly and easily resolve such problems. The fix requires a tedious manual effort.

Conceptually, designers find this block-level design approach extremely attractive. In practice, however, block-level methods have been difficult to deploy consistently, from architectural specifications all the way through final tape-out. The sheer physical complexity of placing even a few blocks, optimizing their shape, and routing system-level wires has already confounded the manual chip-assembly methods in use today. Yet unless designers take these physical design issues into account very early in the development process, they quickly find that their usual development methods lead to designs that can't be manufactured.

Researchers, such as Sylvester and Keutzer at the University of California at Berkeley, have found that the real problems in deep-submicron IC development lie within a few key areas of physical design: the assembly of blocks into a working system and the distribution of clock and power signals across the chip. With designs comprising hundreds of blocks now appearing on the horizon, successful implementation of complex ICs will depend critically on newer methods. These methods called "design plan synthesis" will support block-level designs in an environment parameterized by electrical and physical design constraints.

Design plan synthesis

The design plan synthesis approach allows the designer to predict and influence the performance, area, and power characteristics of the chip long before physical implementation has even begun. It requires no physical design expertise on the part of the architect, because it produces and delivers the required information automatically. In fact, design plan synthesis offers a bidirectional process that provides not only a conduit for the flow of physical information to the architectural designer, but also the flow of architectural requirements to the physical designer.

Using this approach, chip architects can create and explore multiple floorplans quickly and easily and successfully avoid locking into a suboptimal solution too early in the process. The design architecture can thus remain flexible until the design team has adequately analyzed and evaluated critical issues of timing, die size, and power. The technique offers the designer the ability to identify achievable design requirements and to determine how long it will take to meet those requirements.

Most importantly, design plan synthesis helps design teams to overcome the traditional design-test-fix cycle that often proves fatal in complex block-based development. In particular, the process of presenting physical design data early in the process helps those designers who lack physical-design expertise. The information allows them to evaluate critical physical design characteristics such as power or clock schemes, voltage drop, and the electromigration needed to make correct key decisions very early in the design cycle. As a result, design teams successfully produce electrically correct sets of alternative design plans efficiently optimized for power, area, and timing.

Design methodology

Design plan synthesis starts at the very beginning of the chip design process, during the architectural design stage. Chip architects explore alternative design topologies to determine an optimal design plan (see Figure 2). During these early stages, however, most details of the design remain unknown. Yet manufacturability constraints already exist, arising out of early decisions that determined block allocation, timing budgets, area limitations, and a selection of possible target process technologies. Large development projects can thus quickly move to detailed decisions early on for example, assigning certain metal layers for interconnect or restricting others for block usage. In addition, designers may gain access to a great deal of detailed information for some blocks reusable or IP blocks, in particular from the outset of the project. A previous similar design frequently provides a starting point for the new design.

Figure 2 - The new chip refinery

The flow that implements design synthesis takes blocks from specification, through a process of refinement that varies according to the state of the IP, and on to the layout and routing stages.

At this stage, the designer may specify timing, area, and power constraints, effectively meeting two design criteria: to influence the generation and optimization of the floorplans, and to measure and report variances between the constraints and the measured values for timing, area, and power. The designer then partitions the chip into high-level functional blocks and establishes the connectivity between these blocks, automatically generating multiple floorplans. These steps enhance the design strategy, when followed before the blocks contain any internal structural definition.

Even early estimates for unimplemented blocks play a role, because timing specialists can construct a basic timing shell from the estimates. As the design progresses and better data become available, the designers refine the data. Throughout the design process, design team members gain increasingly accurate measures of chip-level speed, area, and routability.

Design plan synthesis combines the best available data for each block- and chip-level constraint, allowing design teams to fully exploit reusable blocks and IP cores. With hard blocks, for example, the strategy incorporates detailed performance data for the block's timing shell early in the planning stage, and presents constraints such as placement or layer usage to the design team sooner and thus more effectively. In addition, architects can explore the impact on chip performance of alternative cores for different memory configurations.

Figure 3 - Automated design plan synthesis

By considering crucial physical effects early on in IC development, designers effectively focus on the best design alternatives.

Drawing on the best available physical design information, chip architects can then build more reli- able what-if scenarios (see Figure 3). The proposed designs explore the impact of high-level decisions such as alternate process technologies, topologies, metal-layer usage, and block planning. Consequently, designers more accurately identify promising design approaches early in the process, avoiding dead-end concepts before committing resources. These design plans may then serve to evaluate timing. Granted, the estimates based on plans at this stage offer only rough approximations, but such estimates promote better design decisions than purely statistical estimates. As structural and physical information then becomes available for each of the blocks, the data incrementally updates and therefore, more accurate estimates of timing, area, and power may then emerge for evaluation.

This design exploration and planning enables architects to deliver the improved data needed to drive key implementation decisions such as process selection, layer usage, block selection, and port/pad placement. In addition, architects can create early timing, area, and power estimates for the chip, as well as refine constraints that need to ripple through the block hierarchy. The results present a tremendously improved starting point for implementation of individual blocks beyond that available with existing manual or semi-automated methods.

Block implementation

Each of the blocks progressively gains definition until all blocks become "hard" (fully laid out and characterized). For example, a block may start out as a "soft" block possessing only interface ports. At some point, structural definition for the block becomes available, and incremental additions turn the "soft" block into a "firm" block. Additionally, if a particular block contains sub-blocks, then the sub-blocks may be floorplanned, compacted, and routed. If the block requires implementation in standard cells, then synthesis and place-and-route processes occur. At some point in time, the block becomes fully defined physically and thus achieves "hard" block status.

Figure 4 - Design planning software

The software that automates design plan synthesis controls the interactions among numerous aspects of the design flow, then generates the appropriate outputs.

This approach as well as the new tools that facilitate the approach complements conventional RTL and gate-level block-building tools (see Figure 4). Because individual blocks exist well within the limits of conventional tools, design team members continue to leverage their investment in best-of-class tools as well as their experience in RTL and gate-level design. From the beginning of block development, designers use specific constraints propagated from the design planning stage to drive their block development tools. For project managers, this method can provide much-improved management of overall chip-level timing, area, and power characteristics.

In fact, at any point during this process, the designer may evaluate layouts for timing, area, and power the later the analysis, the more accurate the conclusions. Using this incremental process provides the designer with a level of predictability previously unachievable using the traditional methodologies that center on logic synthesis and gate-level placement and routing. The designer can then determine the feasibility of meeting all design requirements and the time needed to meet those requirements.

The ability to incrementally update the physical and electrical properties of a block, and to automatically make adjustments to accommodate them, also facilitates concurrent engineering. For example, an initial design plan usually estimates a block's physical and timing characteristics. This information may then be sent to a separate design team whose objectives require the implementation of the block within tight constraints. Different blocks can go to different design teams, and as more accurate information becomes available for each of the blocks, the rest of the team can then have access to that information. In the meantime, the chip-level designers can continue to work on the overall chip design even as the blocks are under development.

In the final stage of block-level design, layout specialists assemble the completed blocks and perform final routing of global nets and block interconnect. Unlike earlier approaches, the design plan synthesis method ensures that this critical stage doesn't present surprises such as unroutable nets or unplaceable blocks to the design team. The ability to synthesize design plans based on continually refined design data helps to increase awareness for the design teams of the impact of various implementation decisions. Consequently, a complex IC design reaches this final stage based on routing constraints entered as early as the pre-RTL planning stage.

Clearly, current manual or semi-automated methods for handling the physical design challenges of today's complex IC designs are failing to deliver design efficiencies in an acceptable fashion or within a predictable timeframe. In contrast, newer block-based design methods do meet the challenges of the emerging IC and system-on-a-chip designs, providing admirable design convergence faster than conventional gate-level design approaches. In fact, using these strategies, design teams can shorten overall development times by 25 to 30 percent and produce more highly optimized designs. As design complexity increases in the coming years toward the 100-million transistor level predicted by the Semiconductor Industry Association's Technology Roadmap, block-based design methods offer the only practical approach for creating manufacturable designs within highly limited development windows.