What Really Happened at DAC?

After a rocky start, DAC '99 rolled on to reveal a number of promising new companies and technologies that should help to chart the course of EDA for the next several years.

by Steven E. Schulz

Okay, so perhaps this wasn't the very best Design Automation Conference of all time. Attendance was down, and humidity was up. Several people commented on the lack of a theme this year. The Intel keynote speech by Paul Ottellini embarrassed the DAC program committee and insulted the audience. On top of that, all those taxicabs parked at one end of the convention center were needed just to ferry attendees to the other end of the convention center! In spite of these criticisms, however, I believe 1999 will be
remembered as a pivotal year for DAC.

Before I delve into technology, I'd like to make one point very clear. The Intel keynote speech, which left so many either disappointed or angry, didn't result from short memory by the DAC program committee (remember Scott McNealy begging engineers to buy more Sun workstations two years ago?). This debacle wasn't their fault--they did everything they could short of canceling the Tuesday keynote. It appears that Mr. Ottellini chose to ignore the DAC policy, and then failed to respond to repeated inquiries by the committee. I have tremendous respect for Intel, but this was an embarrassing lapse in judgement. Although Intel reportedly spent over $300,000 on the speech (complete with a truckful of gear and a crew of 40 workers), Mr. Ottellini might have had better results had he "cold called" us at home during the dinner hour, like any other salesman. To make matters worse, the captive Intel-only demos served only to accelerate the mass exodus from the hall. Now the DAC program committee must put tighter reins on future speakers to keep this from ever happening again. I suggest advance deposits.

By extreme contrast, I found Aart de Geus' keynote speech to be the best in four years. His "System on a Ship" theme was a witty blend of Renaissance history, entertainment, vision, and enthusiasm toward future good times. More importantly, he stated what I believe are the most important trends facing us as we turn the corner into the next decade. He and I may differ over some minor issues in the detailed solutions, but clearly, de Geus spoke as a statesman for the entire EDA industry. Together, these two keynote addressees served as interesting bookends to this year's DAC. Now I'll focus attention on that elusive part in the middle.

Make no mistake, this DAC will be remembered more for what it portends for future design methodologies more than for any "new killer app." Several themes emerged for the first year of what could be a three-to-four-year transition in the fundamental directions for design methodology.

PD captures synthesis

The most significant new trend this year was the integration of physical design and logic synthesis. After eight years of waiting in the wings, physical design is now stealing center stage as it migrates upwards in abstraction. (This trend is hard to miss when Synopsys demos routers!) EDA vendors are realizing that the only way to accomplish timing closure is to merge the logical and the physical views. However, timing closure also requires earlier consideration of physical constraints, even prior to logic synthesis. Thus, physical design is slowly subsuming the back-end portion of logic synthesis, which becomes another optimization step concurrent with all the other constraints on routing.

So what happens to the designers' interactive control of synthesis? It, too, requires tight coupling with physical design, but now occurs through the RTL floorplanning cockpit. Logic synthesis will effectively split into two: the interactive front end coupled with RTL floorplanning and the automated back end that couples with concurrent placement and routing issues. Tera Systems and Aristo, and even Synopsys's new Chip Architect, represent the front end. The back end is represented by Tool suites such as Magma Design Automation, Monterey Design Systems, and Avanti's Saturn/Jupiter. Note that all of these back-end tools include resynthesis technology, and most of them throw away the back-end optimization stage done by RTL synthesis.

Yet the battle isn't yet decided. Clearly, both Synopsys's Design Compiler and Cadence's Envisia synthesis have made major strides in integrating placement into synthesis. Last year, I thought that Buildgates with PKS had a one-to-two year lead over Synopsys, yet Physopt from Synopsys made significant progress in an attempt to catch up. Envisia still has a technology edge with its use of the Common Timing Engine and integration through full placement and routing. Still, Synopsys retains market share, and has tight integration with Designware and other optimization engines. Will the winner in synthesis take all, or is the battle moving to the physical field?

Co-mania

The second major new trend at DAC this year included the wave of interest in hardware/software codesign. While all new technologies require some new design methodology, it isn't clear that designers stand ready to select any one approach just yet. This onslaught of new tools stems from an acceleration of embedded software in system-on-a-chip ASICs--which has become a bigger design issue much faster than many hardware engineers had expected. EDA start-ups offering hardware/software codesign technology include Arexsys, C-Level Design Automation, CAE Plus, Coware, Consystant Design Technologies, Cynapps, Frontier Design, High-Level Design Automation, Lavalogic, Vast Systems Technology, and Y Explorations. That list doesn't even include the biggest vendors, with Scenery from Synopsys and VCC from Cadence.

Much of the discussion regarding these new companies involved comparisons and contrasts with SLDL, creating a frenzy of debate. In many ways, it feels like a return to the early days of HDLs, before standardization took hold and the infrastructure became established. With one exception, these new design languages emphasize function and little else, and thus are leaving open the most critical gap in system-on-a-chip design--the myriad of constraints. However, four of these new companies are cooperating with the SLDL effort, which provides a complementary capability in the form of Rosetta, unveiled to a full crowd during DAC week.

Full chip parasitic extraction made gains this year, as evidenced by Ultima Technologies, Simplex, Frequency Technology, and Monterey. Capacity improvements are astounding, and accuracy continues to improve, albeit at a much slower pace. Frequency Technology is already fielding a solution for inductance, the first to announce such as a commercial capability. The future of VDSM chip design definitely requires these advancements.

Mixed signals?

Analog and mixed signal also made strides this year. One new EDA start-up, Neo-linear, demonstrated some new technology in performance optimization based on constraints. The tool captures the constraints on the schematic, then performs parametric optimization in what amounts to analog synthesis. Improvements in performance of several orders of magnitude are possible using very clever algorithms at the Spice level (with tools from companies such as Antrim and Synopsys's Epic Technology Group).

On the standards front, the new VHDL-AMS analog and mixed-signal language received major support from analog simulation leaders Analogy, Mentor Graphics, Veribest, and FTL Systems. Analogy now offers the VeriasHDL single-kernel simulation environment, integrating all abstraction levels of simulation with support for libraries written in Spice, MAST, VHDL, and Verilog. The FTL Systems Centauri simulator boasts a 10-million-gate-equivalent capacity and incredible speed thanks to proprietary algorithms optimized for use on multiprocessing workstations and servers. The Centauri simulator also converts existing Spice models to VHDL-AMS, as does VeriasHDL and a freely downloadable translator from the University of Cincinnati. In addition, there's a new web site dedicated to nurturing this environment (www.vhdl-ams.com).

Of course, IP and design reuse continue to be hot topics. It appears that the hard-IP suppliers are focusing more on software programmability and customization around the core environment. Companies like Tensilica, ARC Cores, and Improv Systems exemplify this trend, which uses software to define or optimize the hardware. Nonetheless, mainstream RISC processor cores continue to dominate, even while they add data flow and DSP-like features to their instruction set and architecture. In general, however, soft IP--because of its inherent flexibility--clearly offers the dominant approach. The real challenge lies in providing reusable test benches to support the flow.

Two new books were touted at DAC, one being a second revision of the Reuse Methodology Manual from Synopsys and Mentor Graphics. Cadence also responded with their own book on platform-based SOC design. I see the books as representing both sides of the reuse equation. The Synopsys/Mentor RMM emphasizes the need to properly design for reuse, while the Cadence book appears to emphasize what designers do to integrate those reusable blocks into configurable and reusable platforms. The latter offers another angle on the "ASIC migration to ASSP (Application-Specific Standard Product)" trend, which requires higher volumes to offset the rising non-recurring engineering expenses in design.

EDA standards and interoperability

This was a good year for standards. DAC saw the unveiling of many new EDA standards, including the Design Constraints Description Language (DCDL), System Level Design Language (SLDL), and Open Library API (OLA/DCL). DCDL now includes a syntax that builds on Tcl to deliver more robust constraints for RTL synthesis, floorplanning, simulation, test, and formal verification. Furthermore, a joint working group is ensuring semantic consistency among these constraints and those being designed as a part of SLDL. The demo was good, but the big question being asked was "when will Synopsys support it?" The SLDL birds-of-a-feather meeting was filled to capacity for the unveiling of Rosetta, a new high-level constraint language for SLI design.

The OLA demo was particularly rewarding, since it utilized a high-performance 0.18-µm sign-off library, including cores as well as synthesis attributes and full functionality using the new "function graph" approach. The initialization loading time in Cadence's Envisia synthesis tool was less than five seconds for a 63-Mbyte total memory image, eliminating earlier concerns over the fundamental performance of OLA. Synopsys chose to use some extra booth space from a recent acquisition as a platform for EDA standards interoperability, and had a lot of fun with their standards trivia version of "Jeopardy." In addition, Synopsys was promoting several of their own formats for standardization. One format is the Vera test bench description language, which seemed to meet with a lukewarm response. The other is Scenery, a set of C++ class libraries used to describe concurrency and signal semantics as part of the methodology for their Scenic codesign tool.

From Avanti to Magma, Monterey, Sapphire, and even Genedax, it has recently become popular to advocate the "common integrated database" and data model. Many people certainly recognize the need to achieve concurrent tradeoffs in the physical optimization space, yet multi-vendor plug-and-play isn't yet even close to a reality. This unfortunate impediment will make integration even more challenging over the next several years. Perhaps the CHDStd standard will find paths for both funding and implementation to address the much-needed solutions.

New EDA technologies to watch

Given the hundreds of exhibitors, I don't claim to provide a comprehensive listing of interesting new EDA technologies. However, a few caught my attention.

Ultima has developed two new products of note: Nautilus for signal integrity and Clockwise for clock tree synthesis. I was extremely impressed with the capabilities of Nautilus, in particular, for identifying cross talk problems that occur from either intralayer or interlayer signal interaction. Both accuracy and capacity claims are very encouraging. Clockwise is based on the concept of "useful skew," which effectively buys headroom for signals on the critical path by allowing positive skew for certain portions of the circuit. The technology requires a holistic look at the relationship between the clock tree and the signals, but the reward is easier clock tree routing because of the reduced constraints, as well as potential improvement in timing and performance. In addition, retiming effects help to reduce the power by 12 to 20 percent in clock routing.

As verification consumes more than 50 percent of the engineering design effort, it's always an important topic at DAC. One clear trend: SLI integration demands that all software HDL simulators be bilingual in our joint VHDL and Verilog world. This bundling approach includes not only both HDLs, but also integrates cycle-based simulation and discrete event simulation algorithms, with automatic selection of whichever one works best. The other mini-trend in verification occurs in the area of hardware acceleration and emulation--pushed by the major trend of embedded software and the need for more coverification. New EDA start-up Simutech offers the RAVE prototyping system, which leverages a standard PC tower architecture with add-on boards for processors and other IP cores. Meanwhile, Axis touted their accelerated RTL simulation using add-on cards to Sun workstations. Aptix is also offering a new emulation platform, and Quickturn has introduced a mini emulation system. Ikos has added a third-generation FPGA-based emulator that integrates Virtualogic software for better utilization of FPGA capacity and hardware/software coverification for SOCs. All of these new products attempt to drive the cost per gate down, and support rapid embedded software development.

Formal verification made impressive gains in equivalence checking, most notably at Verplex, whose tools can verify the data for a 2.5-million-gate design between RTL and gate levels in just two hours. Verplex has also performed a 6-million-gate verification between two gate-level netlists. Chrysalis continues to make advancements towards model checking, and with the definitive moves of Avanti into the front-end design space, it looks like further flow integration is also highly probable. Synopsys has also listened to customers and is making significant enhancements to Formality. New EDA start-up HDAC formally announced their new static verification product Solidify, which supports greater capacity, uses a simpler means to specify properties, and provides greater feedback on results than traditional model-checking algorithms.

While both Tera Systems and Aristo made their big splash at DAC last year, I think the story is becoming clearer this year. Aristo offers automated interconnect exploration at the RT level, raising predictability for timing closure. Tera Systems, with its Teraform tool, analyzes RTL code and restructures the logical hierarchy to optimize for the downstream physical clustering needed to satisfy critical path timing. The result is a new logical RTL hierarchy that synthesizes for better realization of physical design goals. Aristo's automatic block definition, placement, and global interconnect routing from RTL code complements Tera Systems, although both have different floorplanning views. I see both concepts being useful in the future to manage both predictability and optimization for timing, especially important for larger class designs. Furthermore, these could become the new "front end" for interactive synthesis.

Optical Proximity Correction (OPC) became more mainstream this year with support from OPC Technologies and Mentor Graphics. Even more important, however, is the Phase Shift Mask (PSM) introduction from Numerical Technologies. PSM can significantly extend the life of optical lithography down to smaller geometries, but requires consideration during the design phase, placement and routing in particular. Though this complex technology adds more dimensions to the challenges of physical design, the ITRS roadmap predicts that it will be critical for designs of less than 100 nm.

This New Orleans DAC proved its worth. Time will tell how the issues that came to the surface this year become resolved, but we now at least know the areas of focus and overall methodology implications for several more DACs to come.

Contributing editor Steve Schulz is a senior member of the technical staff in Texas Instruments, Inc.'s Worldwide ASIC division in Dallas. He serves on the board of directors of VHDL International and is the executive sponsor of the System-Level Design Language.

To voice an opinion on this or any other article in Integrated System Design, please e-mail your comments to jeff@isdmag.com.