special section

New Orleans the Technical Way DAC '99 covers the design flow from front to back--and then some. So in addition to the business cards, bring your ears, note pads, and pens. by Jeffrey Erickson

The 36th Design Automation Conference offers a record 190 presentations as the EDA industry strives to keep up with the demands of shrinking geometries and shifting profit centers (see "DAC Facts"). This year's conference theme--"Where Tools & Design Methods Meet"--reflects what's perhaps the industry's most nagging concern as it heads into the millennium: how to make EDA tools work with each other and with the new design flows, especially given the increasing specialization of the tools and the compression of the flows.

The conference formally begins on Tuesday, June 22nd at 9 AM with Paul Otellini's keynote address, "March of Technology." The executive vice president of the Intel Architecture business group, Otellini offers his views concerning the trends driving the computing industry in general and design automation in particular, emphasizing the role of Intel in both. Thursday's wrap-up keynote speech features Aart de Geus, the chairman and CEO of Synopsys. His speech, "EDA to the Rescue of System on a Chip," explores the challenges that face the EDA industry and its customers as silicon capacity increases and more functionality is packed onto each chip. Even before the opening gavel, on Sunday, June 20th the women working in EDA meet for their annual workshop (see "The Women's Workshop").

On the embedded systems track
In response to the growing importance of systems on a chip, DAC has added a Tuesday mini-track on embedded systems software, as part of the larger design methods track. In session 5, "Hardware and Software in Embedded System Design: Shipwreck, Love Boat, or Ships Passing in the Night," a panel consisting of embedded systems designers and EDA tool developers discusses the designers' emerging requirements for EDA tools. Panel members represent Hewlett-Packard, Intel, Synopsys, the University of California at Berkeley, and Wind River Systems.

In special invited papers, session 9 examines operating systems, middleware, and protocols for networked embedded systems. Topics include "Distributed Application Development with Inferno," "Embedded Application Design Using a Real-Time OS," "The Jini Architecture: Dynamic Services in a Flexible Network," and "Networking the Home--Wireless Technologies and Protocols." Session 14 covers compiler and instruction set architecture interactions for embedded processors. The first paper, "Customized Instruction Sets for Embedded Processors," argues that the push toward standardization of architectures will soon be going in the reverse direction: We'll eventually see far greater specialization of embedded architectures for specific use. Next, "A System-Level View of Hardware/Software Tradeoffs" observes that great system-level innovations come from cooperation between software and hardware designers who keep the total system foremost in their mind. Finally, "Next-Generation DSP Software Development Tools" covers the latest contributions to the development of DSP software.

The topic of embedded systems comes up in other sessions as well. Session 8, "System-Level Power Optimization," offers papers on "Memory Optimization for Low-Power Embedded Systems" and "A Low-Power Hardware/Software Partitioning Approach for Core-Based Embedded Systems." Session 44 discusses modeling techniques for achieving design reuse. The first two papers focus on interface-based design using VHDL and object-oriented modeling, whereas the last two describe the use of Java and Java beans for system modeling and reuse.

Session 46 looks at DSP software implementation issues from the system design to the code-generation level. The first paper, "Synthesis of Embedded Software Using Free-Choice Petri Nets," deals with the scheduling of concurrent specifications for multirate applications. The second paper discusses the important issue of memory size estimation for video applications. The next looks at optimization of code generation for irregular architectures. Short papers discuss performance analysis of DSP code and describe a software development environment for DSPs--including scheduling, debugging, and performance analysis.

Wall-to-wall paneling
The session 5 panel is just one of seven panels offered during the week. Following Tuesday's embedded systems panel comes session 15's panel, "Functional Verification: Real Users, Real Problems, Real Opportunities," hosted by the editorial director of ISD and Silicon Strategies, Jonah McLeod. The panelists--designers of cardiac pacemakers, communications satellites, computer servers, networking equipment, and IP--begin by dissecting the bottlenecks in their verification processes. Are simulators too slow? Or do test vector generation and coverage analysis consume the most time? The panelists will present ideas for new EDA products that might accelerate verification, and then discuss what compromises they'd accept in order to achieve that acceleration. Would they learn a new HDL? Restrict their design styles? Forsake legacy designs?

Wednesday's panels begin with session 20, "Cell Libraries--Build vs. Buy, Static vs. Dynamic," chaired by Kurt Keutzer of U.C. Berkeley. The panelists, who represent IP and silicon vendors and users, discuss the variety of cell library choices and debate when designers should use each available source. Chaired by Paul Franzon of North Carolina State University, session 25--"Parasitic Extraction Accuracy: How Much Is Enough?"--addresses the trade-offs between different approaches to achieving sufficient extraction accuracy with reasonable run times. Should we give the priority to fast, very accurate extraction, or should we rely on a 'flow', which uses higher-level information to filter nets before extraction? Alternatively, do sensible design rules reduce the need for interconnect extraction? How do we best address such advanced needs as handling process variation and inductance? What does the term "extraction accuracy" even mean when evaluating the alternative approaches?

Wednesday's panels conclude with session 30, "MEMS Design and CAD: beyond Giga Transistors," chaired by Kristopher Pister of U.C. Berkeley. Existing MEMS products boast more than 1 million electrical and mechanical components on a single chip. MEMS CAD tools are now beginning to leverage corresponding decades of IC CAD expertise to address the unique electromechanical codesign problems from the physical through system-level design. The panel begins with a tutorial introduction provided by Al Pisano, director of the Darpa MEMS program, followed by a discussion by MEMS CAD tool developers and users.

Thursday concludes the technical program with a pair of panels. Andrew Kahng of UCLA chairs session 45, which addresses the impact of subwavelength lithography on design flow. The panel will discuss the design implications arising from techniques used to control subwavelength lithography, beginning with an embedded tutorial on subwavelength mask design techniques and their effect on the IC design process. The panelists then debate the extent of the impact on IC performance, design flow, and CAD tools. Session 55, chaired by Richard Goering of EE Times, addresses the question, "What Is the Proper SOC Design Methodology?" Over the past year two distinct answers have emerged regarding SOC design methodologies. The Reuse Methodology Manual posits that designers can effectively use a logic synthesis-based design methodology to develop systems on a chip. An alternative methodology, in contrast, focuses on integration (or "reference") platforms and the customization of the basic application-specific platform through the addition of selected soft and/or hard blocks of IP. The panelists debate the merits of these seemingly incompatible proposed methodologies.

System design
The discussion of system design begins in session 3, which focuses on approaches to IP-based design. It starts with an invited talk outlining the issues in IP-driven design methodology, and the first paper describes an integrated system for distributed embedded system design. The second paper details an approach to virtual simulation of distributed, Java-based IP models.

The increasingly important topics of system-level verification and testing are covered in session 33. A group from IBM's Haifa lab in Israel is presenting a paper on a methodology for verification of a system on a chip (see that group's contribution to this issue, "Tackling the System Verification of a Network Router," p. 38). The other papers discuss an embedded in-circuit emulator synthesizer for microcontrollers and microprocessor-based testing for core-based systems on a chip.

On Wednesday morning, session 19 presents four papers concerning DSP design techniques and implementations, including a pair of design contest finalists: "Implementation of a Scalable MPEG-4 Wavelet-Based Visual Texture Compression System" and "A 10-Mbit/s Upstream Cable Modem with Automatic Equalization." The other two papers include detailed discussions of power efficiency and accurate memory organization feedback.

Session 24 continues the theme with a series of papers on system-level design methodology and case studies ranging from vertical benchmarks for CAD to the fast prototyping of a multiprocessor design and the verification and management of a multimillion-gate embedded core design. Session 29 focuses on system-level specification techniques. Topics include a specification language that combines C and Esterel, a model for representation of functional variants in systems with reconfigurable components, a Verilog-based specification framework, and a constraint management methodology. Session 51 deals with the instruction-level design of Application-Specific Instruction Set Processors (ASIPs), and includes papers on a methodology for accurate performance evaluation, a machine description language for cycle-accurate models of programmable DSP architectures, and exploiting intellectual property in ASIP designs for embedded DSP software.

Doctor--more tests!
A large group of sessions deals specifically with the increasingly thorny problem of making sure that a design works as intended. One group concerns itself with logic and functional verification and simulation. Session 10, on the functional verification of microprocessors, presents two long papers, "Verifying Large-Scale Multiprocessors Using an Abstract Verification Environment" and "Functional Verification of the Equator Map1000 Microprocessor." Short papers discuss the coverage-directed generation of test programs, the verification of a microprocessor using real-world applications, high-level test generation for the verification of pipelined microprocessors, and the development of a validation suite for the PowerPC architecture.

Session 18 covers three distinct areas in symbolic model checking. The first paper presents a novel technique to analyze the coverage of properties verified by model checking. The next two papers discuss improvements in symbolic reachability analysis, whereas the last presents the application of a SAT solver to model checking. Session 38 presents methods for generating RTL vectors and extracting timing information.

Another group of sessions deals with validation and test. Session 37 presents an advanced set of techniques used for test generation and diagnosis. The first paper introduces a technique to handle testing of gigahertz processors; the second, a novel test generation technique using compaction and an iterative process. The third paper provides a new technique for diagnosing multiple errors. To help solve the challenges of BIST, session 42 introduces techniques that include synthesizing data paths for self-testability, increasing fault coverage of Scan-BIST by using multiple capture cycles and on-chip test sequence generation for at-speed testing.

The technical program includes a number of other sessions of interest, covering topics that range from low-power, analog and mixed-signal, and physical design to device and interconnect modeling. Another group of sessions discusses the impacts of technological advancements; session 40, for example, features two invited papers on new technology directions for 0.18-µm design and beyond.

If you're still hungry for more knowledge, the conference closes on Friday with six all-day tutorials. "Automated Layout and Migration in Ultra Deep Submicron VLSI" covers new algorithm techniques and physical design methodologies that will facilitate high-quality, convergent, automated layout and migration in nanometer CMOS. Rather than solely focusing on raw algorithms and equations, the tutorial conveys how optimization and characterization fit within flows and methodologies, including cell-based design in RTL-down methodologies, and polygon-level design in IP- and migration-based flows. The second tutorial, "Analog and Mixed-Signal Modeling Using the VHDL-AMS Language," introduces the modeling of analog and mixed-signal devices using the VHDL-AMS language, a superset of the IEEE std.1076-1993 VHDL language. Attendees will learn to write portable VHDL-AMS models of moderate complexity and to understand any model written in the language.

Tutorial 3, "Information Visualization: Creating Advanced Visual Interfaces for Analyzing Designs," helps users to effectively design, assess, or utilize software information visualization systems for EDA. The tutorial describes the principles of visual perception and representation that form the basis for effective visualization of large complex data sets. Participants will ultimately be able to recognize the essential elements of an effective information visualization system and understand the significance of a number of successful software visualization tools.

"Overcoming the Technical and Managerial Challenges in Enabling Design Reuse within the Engineering Organization," the fourth tutorial, targets engineering managers and team leaders trying to help their engineering teams to reuse designs effectively. The first part of the tutorial covers rules, design processes, and methodologies for creating, verifying, and integrating reusable soft and hard IP. The second part of the tutorial focuses on the managerial and organizational challenges of internal design reuse.

Tutorial 5, "Embedded Memories in System Design--from Technology to Systems Architecture," aims at system and architecture designers dealing with systems that include large amounts of memory, and at system-level design tool developers and researchers who look at design methodologies and tools that can support embedded memory application design.

The sixth tutorial, "Built-in Self Test for Systems on a Chip," presents state-of-the-art BIST technology, practices, and automation tools. It discusses compelling reasons in favor of and common barriers to BIST adoption, providing a comprehensive coverage of structured design for testability techniques based on scan, guidelines for design of BIST-able cores, and techniques for random pattern testability. A detailed presentation of the most popular and effective BIST architectures for random logic covers generators of patterns, compactors of test responses, and controllers.

To voice an opinion on this or any Integrated System Design article, please email your message to jeff@isdmag.com.

integrated system design  June 1999