editorial

Got VDSM? Cooperate! Porting the design of a microprocessor from bulk to SOI demonstrates the need for ever more accurate models. Only systematic interaction can meet the new standards. by Tets Maniwa

As semiconductor processes move toward finer lines and higher complexity, some interesting trends appear. First, the processes seem to be converging, with smaller differences between fabs for a given feature size in the standard logic process. That trend is partially driven by some of the process development work moving from the IC manufacturer to the wafer processing equipment supplier, who would prefer that everyone use exactly the same operations and sequences on the equipment. At the same time, the processes are becoming more complex, with some starting from a standard base process that receives modular additions for the nonlogic processes: analog, various memory types, and other special-purpose functions. Those special functions require more detailed models and greater model accuracy to match the expected silicon performance.

Second, the new processes are coming on-line more quickly, creating the need for interim models and greater interactions between the design and process communities as they adjust the process for higher manufacturing yields. One example of the level and complexity of interactions among the various disciplines in engineering necessary to develop a new process technology and integrate it into a design and production environment is IBM's development of a 550-MHz PowerPC in a silicon-on-insulator (SOI) process. Although the process development started some time ago, the circuit design started less than two years ago. The various groups were located in different areas of the country, making the interactions between the design and process groups even more important. The magnitude of the changes--retargeting a microprocessor design from a bulk CMOS process to SOI--is much greater than the changes caused by the transition to a deep-submicron process from a larger process. The information exchange needed for the SOI conversion is much higher than the migration to just a finer-line process requires.

According to Ghavam Shahidi, SOI senior program manager at IBM's Microelectronics and Research Divisions, while the process group was migrating the process into the manufacturing areas, they forwarded the characterization data to the design groups for evaluation. The designers identified characteristics in the models that created difficulties in designs, such as floating bulk effects and bipolar parasitics, and then the process engineers worked to minimize the anomalies within the constraints of producing a manufacturable process.

Some of the early test circuits showed very good correlation between the models and the silicon, greatly reducing the risk and uncertainty in the designers' view. The information allowed the designers to develop new circuit topologies to address the unique characteristics of the new process and still meet their short time-to-market requirements. Nor did the level of interactions between the design and process development groups slight the efforts of the other engineering disciplines--like characterization, modeling, and reliability--that were also intimately involved in the transition work.

Finally, as the devices go through their various modifications, the models change to reflect the new device parameters. The most important task in this stage is to ensure that the physical and electrical changes don't ripple through the whole design, damaging the completed portions of the design. It's critical to minimize the required testing and, of course, redesigning. Some small amount of verification through technologies like static timing analysis is acceptable, but a full regression analysis to confirm functionality and timing--especially in the dynamic logic circuits--isn't.

The level of interaction between the silicon technologists and the design groups is becoming more necessary and important for everyone working at the nanometer level. Although the generic processes are converging, the detailed specifications and device parameters can vary enough from fab to fab to wreak havoc on some designs. To minimize the impact of device parameter variations on circuit performance, designers must become much more actively involved in the device characterization and model extraction issues. Designers need a partnership of fabs, extraction and modeling groups or services, library developers, and EDA tools to facilitate the constant immigration of the most up-to-date models. Only then will the final circuit simulations correlate highly with the delivered silicon.

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integrated system design  April 1999