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Interconnect Verification Forms the Linchpin of a DSL VDSM Design A successful very deep submicron communications design project hinged on accurate extraction and characterization of the parasitics. by Ravi Swami and Babu Mandava

Exploding Internet activity continues to fuel the need for faster transfer of large chunks of information, but the bandwidth limitations of data communications currently impedes the full promise of multimedia computing. The company that can quickly create digital subscriber line (DSL) chip sets for mass deployment of central office, personal computer, and customer premises networking products, though, can capitalize on the tremendous market of telecommunications and PC industry OEMs.

To address the complexities of our DSL design, our design team at Centillium began with a careful and deliberate planning process, making decisions about tools, methodologies, and outsourcing. In particular, our management of VDSM parasitic effects through thorough and accurate interconnect extraction and analysis was of critical importance. Likewise, separating the project into two distinct phases--cell and block design and verification followed by a similar process that dealt with the full chip--kept our design flow clean and focused. Assisted by our silicon vendor and a set of interconnect verification and other EDA tools, we needed just 11 months to bring our chip to a successful first-pass tape-out.

When we set out to develop the Copperlite chip set for DSL broadband communication applications, we knew we had to get to market fast. The DSL market was emerging rapidly, and the new G.Lite standard specification for DSL communications promised to accelerate the technology's acceptance by simplifying its installation for home and business users. The performance and density of 0.25-µm silicon technology also presented the opportunity to deliver the higher-speed data transfer and communications bandwidth that a rapidly expanding universe of Internet users is desperately seeking.

Delivering advanced DSL capability to market rapidly, however, presents significant design challenges. DSL technology, even in its lower-bandwidth G.Lite form, is complex to implement, combining analog and digital functions running at high clock speeds (150 to 200 MHz) with low-power operation (2.5- and 3.3-V supplies). It involves the integration of a vast amount of functionality: An eight-port DSL card or board can require as many as 30 separate devices. In addition, rapidly evolving telecommunications standards make designing a hardware product that is immune to premature obsolescence a particular challenge.

Meeting DSL cost, function, and performance requirements also demands the use of very deep submicron silicon. Complex interconnect parasitic effects that we could routinely ignore in technologies above 0.35 µm play the dominant role in VDSM circuit performance. VDSM interconnect parasitic effects and low-voltage operation can create coupling and voltage drops that can easily prove fatal to a design. Interaction between layers and signals is so complex that traditional manual analysis methods are impossible to apply. So we automated as much of the process as possible.

The complete Copperlite system is a two-chip set consisting of an analog device and a multimillion-transistor digital device. The digital IC handles modulation and demodulation, framing, signal processing, and communications. It contains multiple logic blocks, multiple analog elements, and on-chip memory, as well as a specialized DSP engine. Before embarking on the design effort for the complex SOC, we carefully planned our development methodology.

Defining a methodology

To meet our performance and integration goals, we targeted our design to 0.25-µm semiconductor technology with multiple metal layers. Although the project was Centillium's first, our design team had previous experience with 0.25-µm processes. That experience had taught us that designing for VDSM processes--especially a dense, high-performance design like ours--means controlling overdesign. We also knew that highly accurate interconnect extraction was therefore crucial to our success, since inaccurate extraction could force us to significant overdesign--which we couldn't afford--to guarantee performance. We thus planned from the beginning to take extra precautions to manage the parasitic effects associated with VDSM interconnect by paying special attention to verification of the physical layout--in particular, the power grid, clock, and signal nets interconnecting the entire chip.

Figure 1	DSL SOC design flow
A full-custom design methodology was employed to realize the 0.25-µým digital DSL SOC. Parasitic extraction and analysis at the block and full-chip levels was used extensively to avoid overdesign and meet the stringent performance requirements of the DSL market.

Early on, we determined that the project would require a full-custom, customer-owned tooling design approach. Given the complexity of the design task and the verification challenges posed by VDSM silicon, we reasoned that control over our entire design flow was critically important, too. The need for a full-custom COT design flow also stemmed from the stringent performance requirements of our system, which dictated that we custom design a number of critical cells--even such major blocks as the DSP core. Protection of our intellectual property also motivated us to keep full control over the flow and the design content.

The narrow market window for DSL products, coupled with our desire to be the first to market with a G.Lite DSL solution, placed tremendous pressure on us to turn the design quickly. Thus we established an aggressive design goal of eight months from system definition to tape-out. Given the constrained resources of a start-up, to achieve that goal we relied upon support from vendors to extend our resources. We partnered with our silicon vendor to help extend our third-party library's memory functionality. In addition to designing and characterizing our custom memories, our silicon vendor provided design support to speed our physical implementation phase. We also outsourced the full-chip parasitic extraction as well as the power grid and clock skew analysis to help us meet our design schedule and free up CPU resources during the final, critical weeks of our design effort.

To minimize delays in our product development cycle and the risk inherent in adopting new tools, we decided to employ an industry-standard commercial EDA tool suite from the onset of our design project. We selected proven, off-the-shelf, best-in-class tools for every point in the design flow. We used Verilog and the VCS simulator and Design Compiler from Synopsys. For physical layout, we used place-and-route and DRC and LVS tools from Cadence Design Systems. For postlayout static timing analysis, we used Cadence's Pearl. At the transistor level, we performed critical-path timing analysis using Synopsys's Pathmill and Hspice from Avanti. For the critical interconnect verification (extraction and analysis) process, we selected Fire & Ice, Voltagestorm, and Clockstorm from Simplex Solutions. Their unique capabilities include full-chip 3D-extraction accuracy as well as full-chip power grid and clock skew analysis and visualization, which are critical to the success of a design of this size and complexity; they also interface well with the other tools in our flow.

New chip on the block

As noted earlier, we executed the design flow employed in developing the digital SOC in two phases, first designing and verifying cells and blocks and then synthesizing and verifying the full chip (see Figure 1). Central to each phase was a thorough verification process based on highly accurate interconnect extraction. Our tight performance requirements mandated a concerted verification effort at the block level, particularly for such elements as our complex DSP engine, which contains many high-speed datapaths. We wanted to uncover any problems within blocks before we got to the full-chip level, where cross-chip assessment of IR drop and clock skew are particularly critical.

After defining our system and partitioning it into blocks and subblocks, we simulated the behavioral models using the VCS simulator. We identified critical cells and blocks that would require custom layout, designing them using Cadence layout tools and Hspice for functional simulation.

	Block-level flow
Critical-path timing analysis at the block level involved parasitic extraction to produce back-annotated Spice netlists, which were fed into timing analysis and timing model generation tools.

At that point, we took the layout of the custom cells and blocks--as well as the synthesized blocks of third-party standard cells--and began block-level verification (see Figure 2). For critical-path timing analysis, we extracted transistor-level (white-box) parasitic data from the cells and blocks using Fire & Ice. First, we extracted geometries, devices, and connectivity information from the layout of the block or cell to be analyzed. Using our GDS-II and basic command file input, Fire & Ice automatically generated a flat transistor netlist, node and device locations, connectivity, and a geometric database for use by downstream characterization and analysis tools. We also used the information to validate the scripts we used to place vias and connect the power grid within the blocks.

Next, we used Fire & Ice to extract parasitic resistance and capacitance information. We back-annotated that information to the block schematics and Fire & Ice generated Spice netlists with back-annotated RC data that we could readily plug into our critical-path timing analyzer and timing model generator. We then used Hspice and Pathmill to perform postlayout simulation, timing model generation (for static timing analysis), and critical-path timing analysis.

We completed the block-level verification process by performing the static timing analysis. Out of our LEF/DEF input, Fire & Ice extracted connectivity and cell-level (gray-box/black-box) parasitic data, then output DSPF/RSPF. The DSPF/RSPF data, along with the timing models derived from Hspice and Pathmill, formed the input to our static timing analysis tool, Pearl.

Whole-chip surgery

After verifying the individual blocks, we started full-chip design, which consisted of synthesizing the full-chip layout and verifying the full-chip power grid, clock skew, and timing. Design Compiler facilitated the straightforward linking of individual blocks and synthesis of the full chip. We then handed off the design to Simplex for full-chip interconnect verification (see Figure 3).

As with the block-level extraction, Fire & Ice extracted geometries, devices, and connectivity from the GDS-II layout. Greatly improving the speed of extraction, Fire & Ice took advantage of the highly hierarchical and repetitive nature of our design when extracting the layout netlist. For example, it processed each standard cell or block appearing multiple times only once. At this point, the tool produced--along with the flat transistor netlist and node and device dumps--a full-chip connectivity and geometric database in the form of "stripes," or physical partitions of the chip.

Next, Fire & Ice extracted interconnect parasitics from the stripes. To speed the extraction process, the tool sends each stripe to a separate CPU. It also manages the abutment of data at the stripe boundaries, eliminating the loss of accuracy caused by boundary effects. The distributed-processing technique, as a result, ensured the highest level of extraction accuracy for our complex multimillion-transistor VDSM design, yet still produced results overnight running on multiple CPUs. Effectively, extraction with Fire & Ice gave us the turnaround of 2D extraction solutions, but with full-chip 3D accuracy.

For power grid analysis, Fire & Ice extracted the resistance within the power grid. The tool preserves complex resistance mesh networks, such as 90(infinity) corner resistance and via arrays, thereby producing a very high level of accuracy. To handle clock skew analysis, the tool also extracted capacitance by geometrically analyzing each net in all three dimensions, then feeding the parameters to its 3D analytical models for highly accurate capacitance calculations.

Figure 3	Full-chip extraction and analysis flow
The full-chip extraction and analysis process used Fire & Ice, Voltagestorm, and Clockstorm to assess the IR drop within the power grid and the clock skew across the chip.

The tool then merged all the completed stripes to form a single RC database. Voltagestorm and Clockstorm then used the output to perform full-chip power grid and clock skew analysis.

Using the transistor models and layout netlist generated by Fire & Ice, Voltagestorm performed simulations to determine the device currents. It used the tap current data from the simulations, along with the resistance database from Fire & Ice and the specified exact locations and values of the power supplies, to solve and analyze the power network. The tool then generated graphical views and thermal plots for interactive and visual analysis. For our design, the resulting plots showed that IR drops were evenly distributed and concentric around the chip, with the highest drop in the middle of the chip but well within our tolerances (see Figure 4). The findings indicated a well-structured power grid that would require no further optimization.

Next, we used Clockstorm to perform clock skew analysis. With the root clock location manually identified, Clockstorm automatically determined the stages of the clock. Our design contained multiple clock domains and clocks split across different blocks, so clock skew analysis was a critical aspect of full-chip verification. The automatically generated plots and reports revealed that all of the skews of our clock network lay within acceptable tolerances. As at the block level, we completed the full-chip verification process by performing static timing analysis.

A successful effort

The tools from Simplex provided the capacity to extract our large GDS-II files with the accuracy that's essential for meaningful analysis of full-chip power grid and clock distribution. Accurate extraction also saved us from needless overdesign, allowing us to coax every last bit of performance from our process.

Thorough extraction and analysis, at both the block and full-chip levels, gave us confidence that the design we were taping out would meet our speed and reliability goals with no surprises. The extensive, full-chip level analysis took only one week, letting us meet our tight tape-out schedule.

Our design effort was a success: The silicon worked the first time and met our performance goals. Although our original design cycle goal was eight months, we found that plan too aggressive. In the early stages we spent more time defining our methodology than we originally expected, but the design process itself proceeded without glitches or delays, allowing us to turn the multimillion-transistor design in a total of 11 months, from definition to first-pass tape out. In any case, we still achieved our most important goal: We were the first to market with a G.Lite DSL solution.

Ravi Swami is the design manager at Centillium Technology, Inc., in Fremont, Calif. He has 10 years of IC design and verification experience, mostly in high-speed custom design.

Babu Mandava, director of IC design at Centillium, has more than 12 years' IC design and design management experience in the semiconductor industry. He holds one U.S. patent.

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integrated system design  March 1999