Feedback

A forum for readers to speak their mind on issues that are important to the design community

The costs of production

To the Editor:

I just finished reading your editorial on EDA tool prices ("What's a Reasonable Price for EDA Tools?" June, p. 8). As someone in an EDA startup, I appreciate your analysis. We're in the middle of a licensing agreement with a large customer who tried to use the argument that profit margins in the EDA industry are huge because of our low production costs. He failed to understand the large amount of time and money necessary to bring the product to market.

Tallis Blalack
President
Snaketech US
San Jose

The price is right

To the Editor:

I disagree with your editorial's premise. I have been designing board level devices for over 20 years and think that EDA tools, like everything else, are worth exactly what the market will bear paying for them. I personally use DOS-based Orcad Schematic, Tango Route Pro, and Tango PCB. I chose these after buying others that claimed to be more fully integrated, but performed poorly. I think that Microsoft's push to get engineers and designers hooked on NT will fail. I soon will be running my DOS tools under Caldera Linux 2.2. None of these tools are supported. I have personally cracked the Tango tools so that I can use them without the dongle. I paid Tango $900 over two years for maintenance on their tools. On two different occasions when I had technical questions, no one there was familiar with the product. The autorouter I purchased from them was someone else's product and they wouldn't even tell me who I could call for support. If Sears thought that to exist they would need to resell you new Craftsman tools every year, they would have gone broke long ago. As EDA vendors go broke and are bought up, I feel no sorrow for them.

Senior engineer at an
aerospace company

Tweaking parasitics

To the Editor:

I have detected a couple of errors in "Understanding Encroaching Parasitics Can Help to Ensure Signal Quality" (June 1999). On page 32, the second paragraph states that "any increase in C causes a corresponding decrease in the transition times." I believe that "decrease" should be "increase." Using the example in the article, 0.2 mA = 10 fF X 2 V / 100 pS, if current and voltage are held constant and 10 fF is increased to 20 fF then time increases to 200pS.

The table on page 34, "Extracted Line Parameters," includes a Spice capacitance matrix. Elements C11 and C21 look incorrect. C11 is the total capacitance for Trace and should be larger than Trace1 and Trace2 (C22 and C33, respectively), because of the lateral coupling to both outside conductors. C21, the capacitance between Trace and Trace1, should be 0.057365 and not 10.057365.

Roger Tucker
Member of technical staff
Vitesse Semiconductor Corp.
Camarillo, Calif.

Get thee a service pack

To the Editor:

I just read the article located at www.isdmag.com/Editorial/1998/SpecialSection9807.html. In one of your tests, Synopsys Design Compiler crashed and kept the swap space. This is an NT bug that is fixed in service pack 4.

I run Matlab and it has the annoying habit (bug) of grabbing all the memory sometimes for no reason. And then even if I quit the program the memory would remain unavailable. Service pack 4 fixed this problem as well. Matlab would sometimes still grab all the memory, but I would get it back when I killed the app.

Pasquale Leone
Site manager
Zoran Toronto Lab
Toronto, Ont.

Raise the RAM bar

To the Editor:

Good article covering the benchmarking of Windows NT and Solaris, and just how simulation and synthesis applications stack up when running on different types of hardware and operating systems. However, you talk of using 256 Mbytes of RAM along with 1-Gbyte-RAM-class machines to run the new benchmarks. What I'm seeing are customers moving (on the high end) to machines that contain a minimum of 2 Gbytes and often 4 Gbytes of RAM. These are customers doing synthesis, simulation, static timing, and formal verification of multi-million gate designs. The limitation here stems from the 32-bit operating systems that we have to work with at the moment. Gigabit Ethernet and ultra-fast disk I/O is also a key component, along with heaps of RAM and high MHz. As a side note, these days my laptop PC contains more than 256 Mbytes of RAM.

Tim Schneider
Field applications engineer
Synopsys, Inc.
Phoenix

Those so-called HDLs

To the Editor:

You may have made an unintentional error in your June 1999 editorial, when you said "The EDA companies' resources are mainly tied up in brainpower rather than in physical equipment." The EDA industry appears to have no brainpower to tie up. They thrive on two fundamentally flawed HDLs--Verilog and VHDL--to make tools to patch up their shortcomings. These two languages were designed by persons with no knowledge of chip designs nor of language design basics. The users, the EEs, are like the citizens of the Third Reich, following slavishly what they are given.

Nobody dares to ask why the HDLs are so convoluted. The basic premise was wrong: the language developers shouldn't have tried to apply abstractions like the obsolete HDLs developed during the time-shared mainframe era, with hardware shielded from the user by complicated multi-tasking operating systems. Today's Windows and Unix platforms are micro-mainframes. Just as no good architect can ignore the detailed characteristics of the underlying building materials, no chip designer should ignore the basic cells the so-called "synthesis" tools use to prop up the designers' system. I cannot afford the outrageous costs of the tools that support the convoluted HDLs. I use a small safety subset of ISO Ada that restricts the use of all the non-deterministic constructs the computer "science" types added to the language.

Indeed, the restricted constructs were both inappropriate and unnecessary for programming tactical missiles, as I discovered in the early 80s. In particular, VHDL was based on a lie told in 1980 by the VHSIC program office, which proclaimed Ada was inadequate to be used as an HDL. There wasn't even a practical Ada compiler in 1980 for computer scientists to try, let alone the EE types in the chip design labs. The klugy VHDL entity and architecture ruined VHDL as a programming language, despite the fact that it copied most of the draft of Ada-1980. Very few VHDL users know about that fact because IEEE 1076 VHDL manual carefully never mentioned the word Ada in the main body of the manual. I use the safety subset of Ada because I have a very good Ada compiler, with an integrated assembler for 80x86 that was running on my 386 DOS PC aided by a very well designed editor, Vedit, that was based on EMAC. The whole setup costs literally nothing even after I have replaced the 386 with a 486 motherboard given to me.

I can't use "synthesis" in any case. I am using some circuits in a 16-bit chip I designed in the mid-70s for a missile's digital autopilot. I designed it with manual schematic and mask layouts. I had to use draconian measures to save transistors to squeeze a chip into the only leadless carrier available. One of the circuits I designed used the huge inverter gate capacitance for temporary storage, saving lots of transistors. You can't get any vendor to offer such library cells. Furthermore, both laying out manually and describing with the Ada kernel subset takes little time.

Unfortunately, I am generally viewed as obsolete--but the principles behind good designs don't change. I can't even interest any EDA editor to help publicize this approach. One ESNUG e-mailer responded to me: I teach Verilog and VHDL several times a year but Ada is waaaayyyy too complicated. How can you call that brainpower! If the VHDL that includes Ada is not too complicated, how can Ada, a small subset at that, be waaaayyyy too complicated?" A brain is required to think and reason, and the above statement is proof that the writer attributes too much to the EDA industry. It's possible that if this Ada kernel subset really takes hold, all the simulation and synthesis services will go by the wayside. Of course, it's contrary to EDA industry interests to simplify the HDL used by chip designers. Would the VHDL committee chair say, let's not use VHDL additions to Ada or the non-deterministic part of the copied Ada? He would be chairman no longer. Adding to HDLs keeps the committees going.

The EDA industry can bypass the roadblock of ACM SIGAda members that are collectively against any form of official subsetting that throws away the abstractions the EDA vendors value. They only look down their nose at C but won't do anything to rescue the dying Ada language. They are also both uninterested and unknowledgeable in chip designs, despite the fact that SIGAda has for years been passing out (through Red Hat) a two-CD set that includes VHDL syntax and examples. Tell me how and where I can alert the tool users at least to take a careful look at the kernel Ada subset in a positive manner. They can organize a working group to draft a proposal for ISO to sanction its safety restrictions as a subset for both safety critical embedded programming and for use as an HDL to design the chips for these systems. A standard is crucial to push for tool vendor and user support.

There is a saying: catch them while they are young. The kernel Ada subset is ideal to replace Pascal as a teaching language for first-year students or even high-school students. Component-based design concepts should be instilled early. Neither C nor Pascal support the development of reusable components. And please excuse me for venting my feelings. I am used to the freedom of speech practiced by the handful of EEs-turned-computer-designers in the early 50s.

Sy Wong

Reasonable profit?

To the Editor:

Last year, Microsoft made $500,000 per employee. I would define this as monopoly-profit (highway robbery). Microsoft made--not earned--more than $600 per U.S. household.

Nobody would hand draw waveforms, except those who work for start-ups and small businesses and can't afford to spend $10,000 to $100,000 for a single software application. Small companies carry the burden, which means that we who buy a few hundred pieces of one part pay full price; large companies get the discount.

Small business and innovation is further hindered by component quantity pricing, minimum orders, difficulty in obtaining product info, and so forth.

I am for fair trade and free market and against monopoly or extortion. The free market normally would eliminate extra profit. If a product does the work of 100 engineers, takes 10 engineers to develop and sells for the price of 99 engineers, one engineer earns 9.9 times as much the average.

Money doesn't grow on trees; someone pays what others make. You and I and all of society are picking up the tab.

Nick Bucska
PC Peripherals
Broomfield, CO

Corrections

"Tell Me Again-What Does the 'S' in SOC Stand For?" (July, p. 15) incorrectly identified author Takashi Hasegawa as an employee of Fujitsu Microelectronics, Inc. in San Jose. He in fact works for Fujitsu, Ltd. of Tokyo.

In the "Focus Report: HDL Add-in Tools" (June, p. 54), we misspelled the name of Summit Design's debugging and analysis tool Virsim. Contact Summit at (503) 643-9281 or www.summit-design.com.

The "Focus Report: DFT Tools" (July, p. 48) incorrectly states that Vinod Agarwal of Logicvision prefers embedded test to embedded ATE. The statement should read "prefers 'embedded ATE' to 'embedded test.'"

To voice an opinion on this or any other article in Integrated System Design, please e-mail your comments to jeff@isdmag.com.