Feedback

A forum for readers to speak their minds on issues that are important to the design community

In the beginning

To the Editor:

We at Genesys Testware were disappointed at not being included in your Focus Report on Design-For-Test tools (July, p. 48). We provide manufacturing test solutions for designers of large integrated circuits. Our tools promote test reuse and implement the new paradigm in system-on-a-chip testing, using cores to test cores. Genesys Testware was founded in 1995, has been profitable since inception, and provides only silicon-proven products. We have several customers worldwide.

We are no stranger to Integrated System Design . One of our earliest customer success stories is described in the article "Designers Tackle the Testability of a System-Level IC" (February 1998, p. 38). We are also listed in the ISD Vendor Guide and the vendor listing on your Web site. We have been included in several previous Focus Reports on Design-For-Test tools published by ISD as well as other magazines. I am particularly surprised that we were left out of this report just as we are experiencing huge growth in sales. Please contact me at (510) 661-0791 or bejoygo@genesystest.com if you have any questions about our products. Please visit our Web site, www.genesystest.com.

Bejoy G. Oomman
President
Genesys Testware
Fremont, Calif.

Tool prices too high

To the Editor:

I must take a strong issue with what you say about EDA tool costs ("What's a Reasonable Price for EDA Tools?," Editorial, June, p. 8). My company is a small digital design house ($1 million per year gross) with four engineers who design hardware, software, and FPGAs. The other day I inventoried my company's software tool costs, and the tab for the last 12 months was over $100,000, most of which went toward software maintenance contracts. That is 10 percent of my gross.

So why do I need all of these tools? Well, the main reason is because when I buy a particular tool it has so many bugs that I need to obtain the update patches. A prime example of this strategy is with Orcad. Since they discontinued the DOS version (SDT-386), they have yet to produce a stable version. A partial list of required tools includes VHDL and Verilog simulators (Model Tech, Active), synthesis tools (Synplicity), physical mapping tools (Xilinx, Altera), cross compilers (SDS, Introl), emulation software tools (SDS, Nohau), schematic generation (Orcad), board layout (Mentor), device driver kits (MSDN), installation tool software (InstallShield), and documentation generator tools (PDF Distiller, Timing Designer, AutoCAD).

I have yet to see a tool that made an engineer's productivity increase by 10, let alone 100. Back in 1986, it took us about six months to design, develop, and debug a board. Now, it takes us four months to design, develop, and debug a board, cutting our time by a third. I will grant that the functionality of said board is roughly 2-3 times what it was then. In addition, no tool ever made is going to make an engineer think more clearly.

I have seen many tools that make the mundane tasks more fun. A good example of this is Timing Designer. However, at the cost of that tool, I can hardly justify its further use. Nice? Yes. Necessary? No. Our secretary, who loves art, makes much nicer looking pictures for a lot less money, plus she doubles as a pleasant voice on the phone to our customers.

One company model I like is the Altera "per user support model." Now, $2K per year per seat is something that I can afford. I simply make an "Altera" compile machine and use my network to transfer files. At the per seat cost, each user must save 40 hours per year by having his own copy--not likely. The bottom line is that if the EDA companies expect my business, I'm not going to pay over $5-to-10K.

Unfortunately, all the EDA vendors seem to be carving out a small niche market, so we now need three tools to do the job where one used to suffice. Perhaps a large company with a huge middle management structure can support those costs--but I can't.

Trevor J. Coolidge
Design engineer and owner
Communications and Real Time
Systems of California, Inc.
San Diego

Less for your money

To the Editor:

What you say about tool prices does apply to those designing large digital or mostly digital ICs. They need the tools that can efficiently handle the sheer deign complexity. Even though relatively inexpensive tools can handle design entry and simulation, the implementation of the design requires a system capable of handling millions of transistors.

However, other types of designs are out there. A lot of companies are now designing or considering designing some less complex ASICs for various applications. and don't forget all the analog and mixed-signal ASICs, where the challenge of the design is in the analog circuit design, and not in the number of devices.

I have designed several mixed-signal (more than 50-percent analog in size) ASICs for transducer interface. We started by implemented them as test chips using MPW runs during the research phase of the projects; we now have two designs in production and are working on the next one. Up to this point, we have used some "inexpensive" "low-end" PC-based tools to accomplish the designs--and we were very successful. We used Microsim Pspice for analog and mixed-signal simulation, and Tanner Research L-Edit for layout. For less than $15K, the tools contained the full functionality for this type of design: schematic entry, analog and mixed-signal simulation, and IC layout editing, with LVS and place-and-route capability for digital blocks. PCs have become so powerful that performance issues when compared to Unix workstations are less of an issue now than 5 or 10 years ago.

However, during one of the designs, we started reaching some of the limits of the software, particularly on the layout side, where things started to happen pretty slowly. I got somewhat frustrated, and we started looking for other options. We talked to Cadence, and to obtain the same functionality, we needed to purchase a $250K system! (And even then I think that we would have needed a few "hidden" additional tools to do everything we wanted to do, at a minimum of $15K/tool). In addition, the cost of purchasing one or two Unix workstations and to maintain them, when we are a PC-based company. Of course, we heard several arguments from the sales people: a lot of small companies invest in our tools because they know that they need the best tools, and they will pay for themselves in the long run; your productivity will at least double using our tools; we are the best and the recognized standard in the industry.

Our decision, however, rested on other factors. I work for a small R&D company, and I design maybe one IC per year. The rest of the time, I am involved with testing, other system development issues, and transducer research. Even if my productivity doubled, I couldn't justify the cost increase in the tools. Maybe if I were designing ICs 100 percent of the time, year round?

Right now, particularly since Tanner Research started improving L-Edit again, the tools we are using are quite suitable for the ICs I work on. Since most of the effort goes into designing a high-accuracy, low-noise front-end circuit, the critical design effort depends a lot more on the designer than on the tools he uses. So we are staying with what we have.

As I see it, the biggest problem with the pricing of design tools is the very nonlinear price/performance curve. You can't buy a slightly more expensive system to obtain the added functionality you want; you need to spend 10 or 20 times the amount to get definitely much less than 10 or 20 times the functionality. I hope that in the future, the curve will become more linear, with more options.

Name withheld by request

To voice an opinion on this or any other article in Integrated System Design, please e-mail your comments to jeff@isdmag.com.