programmables

PLDs and Their Users Benefit from In-Field Reconfiguration Options Reconfiguring PLDs in the field offers users customization and allows vendors to provide support without leaving the office. by Barry Flannaghan and Martin S. Won

Hardware engineers have long used PLD reconfigurability during the development stage to allow rapid respins of a design. During initial manufacturing, a reconfigurable PLD solution allows updates and modifications to continue even after the customer has received the shipped product. However, the most ambitious strategies utilizing PLD reconfigurability--strategies involving design changes during the volume manufacturing stage--remain relatively rare, despite the obvious advantages and potential rewards. Besides allowing minor hardware updates to continue, PLD reconfigurability also provides a developer with the means to make major functionality upgrades or modifications to a customer's system. Importantly, users or vendor support technicians can implement those changes using installed equipment at the customer's site. Vendors can, therefore, meet customer needs on an incremental basis, initially with a product that includes a minimal feature set, and later with updates that provide more capabilities. Entire product lines can arise out of a base design utilizing reconfigurable PLDs, resulting in cost savings during both the development and the manufacturing phases.

At Snell & Wilcox, a provider of digital image equipment, we developed a video processor that took advantage of the reconfigurability that PLDs offer. The reconfiguration options available in PLDs allowed us to build a video processor that--depending upon its configuration--could perform a range of functions, including frame synchronization, audio processing, noise reduction, aspect ratio conversion, and color correction. Once our designers mastered the moderate technical requirements for allowing upgrades and modifications, both during manufacturing and after installation at the customer's site, we simplified our own production process while expanding the feature set that we could offer to our customers.

Although PLDs have long been configurable in the prototyping environment of the design engineer's workbench, only in the past few years have they become easily reconfigurable while in their system of operation. In particular, the advent of SRAM-based devices with flexible and rapid reconfiguration options has made in-system changes to PLDs a reality for the system designer. SRAM-based PLDs use SRAM elements to store configuration data that controls the interconnectivity and logical functions of the device. Since SRAM is volatile, this configuration data must be held external to the PLD for loading into the device upon startup or restart. It is possible, therefore, to completely change the operation of the PLD by simply loading in new configuration data. Users can realize completely different functions (and thus product features) by loading different configuration data into the same PLD. Further, employing an intelligent host to control the configuration process makes it possible to reconfigure the PLD even after it's installed in operating equipment, allowing in-field upgrades or other modifications of functionality.

Designing to reconfigure

When creating a product line from a reconfigurable design, the designers should identify the common functionality that the different versions of the product will share, to avoid unnecessary repetition of their efforts. The amount of commonality between the different versions in terms of logical operation and I/O influences the design of the base product. In our case, the products we set out to build share a similar purpose--manipulation of digital video data--as well as a similar I/O requirement--a serial digital interface (SDI). Designs with common or identical I/O requirements can utilize the same PC-board layout, offering great savings in both design development and production costs.

The D1 processor, the base design that we created for our reconfigurable products, consists of SDI input and output devices, two PLDs (Flex 10K devices from Altera Corp.), a microprocessor, and SRAM and Flash memory devices. The ultimate functionality of the different D1 processor products depends upon the DSP operations performed by the EPF10K50 devices, and the look-up tables loaded into several of the SRAM devices. The microprocessor controls the configuration of the PLDs, manages the data held in the memory devices, and handles incoming data for new configurations.

Currently, the D1 processor forms the basis for five products: an aspect ratio converter, a digital picture fixer, a video noise reducer, and two types of synchronizers. The digital picture fixer requires only one PLD, as does the base model of the synchronizer. Designing a synchronizer base model that requires just a single D1 processor allows us to offer an economical option as well as the more feature-rich but costlier upgraded model that employs multiple D1 processors. The PLDs in these various products each use slightly different I/O configurations. The position and function of each I/O pin can be determined for each product configuration, and unused I/O pins on the devices are tristated. The different configurations use anywhere from 40 to 95 percent of the available logic resources in the devices, and anywhere from 4 to 8 of the 10 available embedded array blocks (EABs) for memory functions.

The digital picture fixer uses 75 percent of the logic cells, 35 percent of the memory bits, and 67 percent of the I/O pins available in the 240-pin QFP version of the EPF10K50V device (see Figure 1). The input FIFO, built with EAB RAM, receives data based on the clock recovered from the video signal. Then the FIFO sends that data out with an externally generated clock that the PLL has locked to the input clock. EABs also store curves in the look-up tables (LUTs) that feed both the processing amplifier and the horizontal filtering block. The system loads the curves into the LUTs, then applies the curves to the video data based upon commands from the microprocessor--a microprocessor that the end user, in turn, controls. The data then feeds the picture correction block, which operates on chrominance and luminance to provide the closest legal color in the RGB gamut space. The curves needed to map the YCbCr gamut space to the RGB gamut space require two 128 K x 8 LUTs and external SRAMs. Finally, the data passes through the output format block, which can apply the patterns or logos (stored in another off-chip SRAM) to the video output according to the end-user settings.

Another one of the D1 processor-based products is the video noise reducer. Unlike the digital picture fixer, the video noise reducer requires two PLDs, an input device, and an output device. Similar to the digital picture fixer, the input device for the video noise reducer contains a FIFO composed of EAB RAM, a processing amplifier, and an output formatter that can apply patterns or a logo to the video output (see Figure 2). However, again unlike the digital picture fixer, the processing amplifier in the video noise reducer doesn't apply curves to the data. The majority of the work occurs in the noise filter, which performs low-pass filtering and applies the curves in the nonlinear LUT to the video frame. The microprocessor loads curves into the nonlinear LUT based on the characteristics of the previous frame (which is held in SRAM). Since only parts of the frame may receive the filtering, the system uses padding delays (implemented in EABs) to resynchronize the data before it exits the noise filter. This design uses 41 percent of the logic cells, 20 percent of the memory bits, and 98 percent of the I/O pins of an EPF10K50V device.

The output device of the video noise reducer incorporates several filters, including a vertical filter, a horizontal filter, and a 7-point median filter (see Figure 3). Video memory devices hold the previous frame data for referencing by the filters and the impulse and motion detector. The processor loads the LUT that follows the horizontal filter with curves that are applied to the data. The combiner constructs the output video frame using several adders and selectors. Configurable feedback paths in the combiner allow the microprocessor to direct filter usage and the filtration order of the data, depending on the noise characteristics. This process may cause the different parts of the frame to desynchronize, so the system employs a padding delay composed of two EABs to resynchronize the data, if necessary. This design uses 44 percent of the logic cells, 41 percent of the memory bits, and 63 percent of the I/O pins of the PLD.

Figure 1	Digital picture fixer
On-chip embedded memory implements most memory functions (FIFO and look-up tables) in the digital picture fixer, while larger memory blocks use external SRAM.

As long as they fit into the two PLDs and the card I/O, the number of different products that can evolve from the D1 processor is virtually unlimited. The DSP functions found in D1 processor-based products represent only one type of function that can serve as the basis of a reconfigurable product. Other data processing-type functions--especially synchronous, pipelined operations--are also good candidates. Ultimately, only space constraints limit the kinds of designs that a reconfigurable product can implement.

Figure 2	Video noise reducer input device
The noise reducer input device applies noise filtering to a video frame based on previous frame data stored in an external SRAM device.

On-the-spot modifications

Updates to PLD-based designs installed at customer sites may or may not require the involvement of the manufacturer, depending on the implementation. If the changes are minor, they may not even require the reprogramming of the device. For example, the on-board memory structures of a PLD can hold data that is fundamental to the operation of the device (for instance, coefficients of DSP filters, look-up tables, and instructions for on-board processors). The on-site updating technique benefits from the high memory-to-logic ratios--10 to 12 bits of dedicated memory per logic cell--that are a feature of the largest-capacity PLDs. Users can load these on-board memory structures with new data while the device is in operation, minimizing system interruptions. If the modifications or updates require a reconfiguration of the device, users can easily replace the reconfiguration data. While a simple solution might physically replace the memory device that holds the configuration data, a more elegant solution would reprogram the memory device itself.

To hold the configuration data, the D1 processor uses two memory devices, one based on SRAM, the other on Flash technology. As mentioned previously, an on-board processor controls the configuration of the D1 processor products. The Flash devices store the configuration data. The microprocessor stores its operating code in Flash, but loads it into the SRAM to speed execution. In the field, the microprocessor is able to load new configuration data into the Flash devices. The D1 receives the new configuration files through a network interface known as Roll Call, a proprietary scheme contained in all of the D1 processor-based designs.

Although the D1 processor uses a proprietary network interface for receiving updated device configuration data, users can achieve the same goal with other reconfigurable products by employing various other interfaces, such as PCI. The key to realizing the necessary features for any given product is in the design of the configuration host. Microprocessors, microcontrollers, or other programmable devices can serve as hosts. If the user possesses only a limited set of configuration schemes and sources of configuration data, then a simple configuration host, such as that provided by another PLD, may suffice.

Our designers wanted to support the ability to configure devices from a remote location, so we used an intelligent host that other devices within the same Roll Call network could control. The D1 processor-based designs are therefore modular components of the digital video processing system. We designed these components, or local cards, to fit into enclosures that attach to other Roll Call units or to a PC through an RS-422 connection. This network scheme allows PCs to take control of the individual cards for the purposes of operation and reconfiguration. The PCs can send configuration data to any card in the network, which permits us to deliver new configuration files to end users in any form--including internet downloads, e-mail attachments, or disk-based files--that the PCs can recognize. The scheme also allows the manufacturer to remotely connect to the network and control configuration of the D1 processor-based designs, allowing complete off-site control.

Aggressive passive configuration

"Passive serial configuration" is Altera's term for the method we use to reconfigure the PLDs in the D1 processor. The PLDs act as passive recipients of the data, while an external host (in this case, the microprocessor) controls the configuration process (see Figure 4). Other available schemes configure the Flex devices synchronously or asynchronously with parallel streams of data, or control the process with a configuration EPROM device. Two pins in the Flex device (MSEL0 and MSEL1) are set either high or low.

Figure 3	Video noise reducer output device
In the noise reducer output device, the microprocessor controls the type and order of filtering that the video data requires, based on its noise characteristics.

The passive serial configuration process begins when the processor sends a low-to-high transition on the Flex device's CONFIG pin. The processor then presents the configuration data on the Flex 10K device's DATA0 pin and clocks it into the device serially with DCLK. When the processor has finished its task, the CEO pin on the first device activates the CE pin on the second device, signaling the incoming stream of configuration data. When the second device asserts CONF_DONE, the processor recognizes that configuration is complete. The entire process of reconfiguring the two devices and restarting the card with the updated configuration takes about 5 seconds, during which time the card doesn't output a video signal. (We intend future versions of the product to reconfigure more quickly, using the passive parallel configuration scheme.) The scheme updates the devices individually to maintain the video output of the second device. In total, the process results in a video delay of about 10 frames (less than a half a second).

Figure 4	Passive serial configurationprogrammbles
A configuration host such as a microprocessor can configure multiple Flex 10K devices. The host streams configuration data serially from the memory source through one device and then the next.

For the D1 processor, we wrote code to control the PLD configuration through programming pins that double as I/O pins during device operation. Another option sets up the microprocessor to configure the devices through their connection to an IEEE 1149.1 JTAG chain. This option is convenient if a JTAG chain already connects the PLDs for board-level testing. An available open-source C program, which can be compiled for either 16- or 32-bit processors, interprets device programming information stored in system memory and writes it directly to the TDI, TCK, and TMS wires of a JTAG chain. The test access port (TAP) state machine in the JTAG-compliant device responds to these signals and writes the configuration data to addresses in the PLD. This scheme allows the programming of any number of PLDs along the JTAG chain, even if the chain includes non-programmable devices. More information about this programming scheme--including the programming source code and design files--appears at www.jamisp.com.

Building a reconfigurable product lowered both testing and manufacturing costs. Though our PC board served several products, we had to develop only one test flow, reducing the amount of test engineering resources required. We were able to apply the same ATE tests to all products based on the D1 processor, establishing product differentiation later on during the PLD programming phase of manufacturing. We could thus justify greater investment in ATE.

PLD reconfigurability offers a number of potential benefits to troubleshooting in the field. For example, one of the possible PLD configurations might be a "diagnostic mode" that captures data from the surrounding system. To troubleshoot a problem we could e-mail or upload the diagnostic mode configuration file to a customer, who could then in turn send the resulting data packet back to us for analysis. When combined with the ability to control device configuration from a remote location, this strategy would allow us to troubleshoot the end customer's equipment without physically visiting the customer's location. As with product feature definition, the opportunities for in-field troubleshooting of reconfigurable products are excellent, limited only to the I/O constraints and the capabilities of the programmable devices involved.

Barry Flannaghan joined Snell & Wilcox, Ltd. of Twickenham, England in 1985 and is now technical director of the Liss Research product development laboratory. Previously, he worked for the BBC in a multidisciplinary studio operations role, and as a research and development engineer for the Independent Broadcasting Authority.

Martin S. Won is a member of technical staff at Altera Corp. in San Jose, Calif. He has eight years of experience in digital system designs involving programmable logic devices.

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integrated system design  May 1999