design tools

Modeling Substrate Effects in RF Integration Mixed-signal designers can save a wealth of time and money by simulating substrate parasitic effects rather than waiting weeks for test chips to return from the fab. by Didier Belot and Tallis Blalack

Fierce competition is pushing designs to new frontiers and spawning novel design approaches to reduce time to market and provide products with better performance at a reduced price. Companies must be constantly rethinking their processes and looking for ways to improve their designs--especially in the RF marketplace, where it's critical to obtain peak performance from the available technology. For those designs, we're at a point where traditional approaches are proving insufficient. At STmicroelectronics, we've been looking into recent breakthroughs in methodologies for RF circuit design. The trend toward deep-submicron devices, greater integration, and higher frequencies has forced us to consider various substrate coupling effects.

We've recently implemented new flows that reduce costs and increase efficiency in modeling substrate effects in our designs, thereby taking advantage of developments in the EDA tools arena. By incorporating software capable of creating a model for the substrate, we bypassed resource-consuming fabrication and testing steps. After reviewing the available tools in the EDA marketplace, we chose Snaketech's Layin, a suite of tools for three-dimensional substrate-noise modeling. The tool has brought a number of benefits to our design process, including a streamlined design flow that has saved us significant time, manufacturing costs, and engineering resources. It has also provided us with the flexibility to simulate structures that were previously impossible to characterize. We now enjoy an improved methodology that enables our design teams to quickly develop device models without costly fabrication and measurement steps.

To improve circuit reliability, it's common practice to characterize a set of transistors and generate models that will provide the base for the RF designer's simulations. The characterization process consists of fabricating the device and setting up specific measurements to quantify critical device parameters, which are then included in an electrical spice model. One important measured parameter is the access resistance from bulk to substrate, which influences circuit behavior at high frequencies. Such resistance can shunt signals to ground, provide an access point for noise injection, and modify the device's behavior. Designers must measure those parameters once on each new transistor layout, and then again after a fabrication technology change.

The entire design flow would benefit from avoiding as much fabrication and testing as possible. Fabrication of a few devices is a costly process, and it takes roughly two months for the foundry to deliver the test devices. Performing the measurements and calibrating the results is no easy task either, because the testers must take into account the parasitics from the probes, pads, and interconnect. Modeling those elements requires extra effort and a detailed understanding of the physical characteristics of the design. In every design, careful selection of process technology, power connections, and layout techniques determine the degree of isolation and substrate noise immunity that we can achieve. Our success depends on our understanding the primary tradeoffs involved.

Figure 1	The design flow revisited
The Layin design flow saves time and effort by allowing simulation to take place much earlier in the cycle--prior to the fabrication of test wafers. Fabrication, measurement, and verification of test chips become optional.

Navigating the substrates

Several factors go into picking the best-suited fabrication technology for a specific design. One of the first decisions is to choose the type of substrate, which determines how substrate noise propagates throughout the circuit. Two common types of substrate in commercially available CMOS products are epitaxial and lightly doped; BiCMOS products use a combination of the two.

An epitaxial substrate consists of a heavily doped, low-resistance bulk substrate topped by a lightly doped, higher-resistance epitaxial layer. Unfortunately, epitaxial substrates make it difficult to obtain isolation simply by physically increasing the distances between circuit blocks. Depending on the lightly doped layer thickness, there comes a point after which increasing the separation between a noisy and a sensitive section provides no further benefits. The low-resistivity bulk substrate acts as a short between the two regions. In general, that type of substrate encourages few isolation choices, although adding a backside connection through which currents can sink may reduce the injected noise. The disadvantages of using a backside connection are higher packaging costs and the operating frequency limitations caused by parasitics from the connection.

A lightly doped substrate uses a uniformly (lightly) doped bulk wafer. In contrast with an epitaxial substrate, it's easier to achieve isolation in the lightly doped case because the high resistivity of the bulk attenuates noise signals. However, deriving an appropriate resistive mesh to include substrate effects in any simulation is much more difficult. Nonetheless, lightly doped substrates are less expensive than epitaxial, though CMOS digital circuits commonly use epitaxial substrates to help minimize latchup.

In both technologies, surface implants--such as channel stops--reduce the effectiveness of separating parts of the design. Such implants have a low resistivity and allow noise currents to travel through them. Buried layers in BiCMOS processes may have a similar effect. Designers trying to understand the effects face a significant challenge because the way noise propagates through the substrate changes dramatically, depending on whether the surface and buried implants are broken or not (as they are in the presence of wells, for instance).

Once the designers have chosen the type of substrate, they must carefully consider the use of separate supplies, which can connect to different parts of the circuit or the substrate. It's possible to use a separate supply for an LNA, VCO, or another sensitive analog block, preventing noise interaction through the supply. Depending on the technology, using different supplies to connect to the substrate may benefit the design or may increase coupling problems. The designer must also consider pin assignment and availability: it's generally best to keep pins from different supplies as far as possible from each other in the package.

In addition to the substrate and supply decisions, still another concern is guard rings--low-resistivity contacts that surround sensitive sections and set the electric potential around them. Used with varying degrees of success, guard rings in most cases force currents to flow deeper into the substrate, improving isolation. In other cases they actually provide a path for noise signals to travel. Determining which noise reduction rules of thumb to apply can be difficult, and a lack of knowledge can amplify--rather than minimize--noise coupling.

Understandably, layout and technology tradeoffs don't always present an obvious choice, particularly without the proper means to determine qualitatively and quantitatively the best solution to a specific design scenario. To establish a method to expedite the choices, we searched for a tool that could take into account our process and layout information and provide an accurate substrate model. Such a tool would minimize the amount of overengineering required to ensure a design's proper operation after fabrication while providing time and cost advantages.

Conquering the noisy substrates

Some commercial tools, such as Pisces, use process information to provide device models that include parasitic elements associated with the substrate and the device itself. However, such a tool was of limited use to our design teams because simulation time limitations made the tool infeasible for cell or block analysis. Of no less importance is the tool's limited accuracy: It produces circuit models based on two-dimensional information. We needed a solution that we could easily integrate within our existing CAD environment, that employed a three-dimensional design paradigm to account for various substrate effects, and that could cope with extensive cell and block analysis.

Figure 2	LNA layout analysis
A screen capture of the low-noise amplifier highlights the input transistors (1) that must be correctly isolated from the noise coupling from the output transistors (2) and switch transistors (3).

To solve our substrate analysis problem, we chose Snaketech's Layin, which we've now integrated into our design flow (see Figure 1). Of our criteria for Layin's selection, perhaps the most important was accuracy in the generated models, which allowed us to obtain realistic simulations. Other characteristics that guided our decision were ease of integration into our current design process, adaptability to different technologies, qualitative analysis of layout with respect to substrate noise, and the ability to work with designs of different sizes.

Layin provides a Technology Characterization Tool (TCT) to create a technology description file. The main input into the tool is a set of files describing the silicon doping information for the different structures that compose an integrated circuit. The output summarizes the information required to model the different sections of a circuit. In the TCT, the user can also input parameters that model parasitics that interface to the substrate surface; for example, capacitive coupling from a large pad or the contact resistance of a substrate tap.

Figure 3	Agreeable parameters
The results for the real part of the Z 11 parameter show the tool's model in close agreement with the simulated and measured findings.

Although the tool ships in a stand-alone version, the main Layin tool is integrated into the Cadence environment by way of the Cadence Connections Program, which made it very easy for us to incorporate the tool into our existing CAD flow. Cadence's extracted view displayed Layin elements in what the vendor calls the substrate abstract view (see Figure 2). In the abstract view we then specified the transistors and additional devices we wanted to link to the substrate model. After saving the abstract view, we ran the Layin substrate model extraction. It automatically connected the substrate model to our netlist, so we avoided any additional work before starting the electrical simulations on the circuit. Layin also added several visualization options. We could view a color pattern--overlaid on the design--showing the noise level a node generates at different frequencies, or we could display a perturbing path--the path of least resistance from a noisy node to a sensitive one.

We needed to make only a minimal effort to integrate Layin into the Cadence environment. We mainly set up a file that linked the profiles from the Technology Description File to the layout elements we wanted to model. The new file specified the correct profiles to use under wells, taps, and transistors.

A question of characterization

We have used Layin most frequently for device characterization. For such a purpose, the 3-D model generated by the tool was critical for achieving the required level of accuracy. To verify the accuracy of one of our designs, we fabricated a test structure, then measured and simulated its Z ₁₁ impedance using a Layin-generated model. The structure consisted of a 50-µm x 50-µm N-diffusion square built on a p-type substrate. The structure was surrounded by a 1-µm-wide P+ ring connected to ground; a distance of 1 µm separated the ring from the square. We connected the square to a metal pad to perform the measurements. To obtain more realistic simulation results, we included a model of the parasitics from each metal pad and metal line in the simulation. We measured the Z ₁₁ parameter, characterizing the impedance between the N square and the P+ contact ring, using a coplanar probe and a 0-V bias voltage. Layin's extraction time for this circuit was 8.7 seconds, and the simulation agreed closely with the measurements (see Figure 3).

We also fabricated other structures and took different measurements. In all cases we verified that the simulations correlated well with the measurements. On the strength of those results, we decided that Layin would be able to properly characterize the features we wanted in new devices.

After validating Layin's accuracy, we extended its use to investigate scenarios that can be difficult to test experimentally because of setup and measurement limitations. For example, to obtain the measurements presented in Figure 3, we used a 0-volt substrate bias. The tool allowed us to evaluate the influence of different substrate bias voltages, which was impossible to achieve experimentally.

Figure 4	Working in isolation
The LNA transmission parameter simulations using the Layin substrate model illustrating the isolation obtained between the input and the output transistors (S 12 ) and between the input transistors and the switches (S 13 ).

Large designs can prove difficult to analyze using software tools. Simulation time and computer resource consumption grow in a non-linear fashion as the number of circuit elements increases. For a large design, such as a complex circuit block or a complete chip, certain simulations performed with full accuracy can take an impractical amount of time to complete. However, for a large block maximum accuracy is frequently not a crucial consideration. When we analyze substrate effects from a layout, floorplanning, and block placement perspective, it's more important to obtain a good estimate of where noise is coupling from or to determine the approximate effects of placement options. Once we've established those values, we can perform a more accurate analysis on a specific section.

Layin can run extractions not only on small cells, but also on larger cell blocks and even chips. The difficulty in analyzing large designs with three-dimensional parasitic extraction algorithms stems from the large amount of nets and elements that the model creates. Fortunately, the tool includes features--specifically aimed at large designs--that allow it to increase the extraction speed considerably without greatly reducing accuracy.

We used Layin to simulate some of the parameters of one of our front-end RF chips, a differential input Low Noise Amplifier (LNA). In the circuit layout, we took specific precautions to reduce the noise coupling effects into the input transistors. The noise sources in the circuit are the switch and output transistors. The tool models the transfer functions between output and input--the S ₁₂ parameter--as well as between switch and input--the S ₁₃ parameter (see Figure 4). The ability to simulate those parameters was extremely valuable, because in addition to saving a significant amount of time, it also provided an accurate way to check responses that would otherwise be extremely difficult to measure. Moreover, performing such measurements on the actual chip would have required pads dedicated to the different nodes. Together with the device and interconnect parasitics, the substrate model generated by the tool helped to ensure that the designed product met the specifications. Looking forward, we plan to model the substrate of an entire chip in the floorplanning stage and include substrate models in additional RF simulations.

The new flow we've implemented has reduced the cost and the time required to complete new designs, particularly as we adopt new fabrication processes. The level of accuracy provided by the Layin substrate model has eliminated the need for device fabrication and measurement. We can therefore analyze a greater variety of test structures and evaluate different technologies in less time.

Didier Belot joined the analog and mixed IC development group at STmicroelectronics in Crolles, France as an RF project engineer in 1996. He previously worked for Thomson Semiconductor for 13 years, most recently as a designer of high-speed data communication ICs.

Tallis Blalack, president of Snaketech U.S., has been directing the company's U.S. operations since 1997. His previous research investigated substrate-noise coupling and included the design and testing of two experimental chips.

To voice an opinion on this or any Integrated System Design article, please email your message to jeff@isdmag.com.

integrated system design  May 1999