When TTL device functions migrated to CMOS processes, the convention remained for a voltage greater than 3.25 V to represent a ý1,ý and a voltage less than 0.7 to represent a ý0.ý CMOS provided a rail-to-rail signal swing; interfacing from TTL required that a pull-up resistor on the output of the device should match the output swing of the TTL to that required by the CMOS. The signal levels didnýt cause any problems with the rest of the system because system clocks were 5 MHz and edge rates were greater than 10 ns.

Now, with system bus speeds at 100 MHz in a desktop PC and the edge speeds less than 1 ns, the issues of data transfer become intertwined with the signal transport functions. A signal frequency of 100 MHz sits in the middle of the FM band, definitely in the RF signal domain. A rise or fall time of a nanosecond translates to equivalent frequency components well in excess of 10 GHz.

Once signals move into the RF domain, they need more RF-type analysis to determine if any environmental conditions have degraded the quality of the signal. The adverse effects associated with the high-speed designs can include signal integrity, electro-magnetic interference (EMI) and electro-magnetic compatibility (EMC), noise immunity, ground bounce, and supply droop.

Measurements of signal integrity indicate the relative fidelity of the transmitted signal. As signals move further into the high-speed domain, the transmission media begins to exert a greater influence on the signal quality. Non-ideal media composed of resistance, capacitance, and inductance cause delay, while mismatches in characteristic impedance causes reflection. The signal reflections either constructively or destructively interfere with the original signal and turn clean, fast transitions into very ýdirtyý waveforms.

Electromagnetic compatibility (EMC) and electromagnetic interference (EMI) are the circuit responses to influences which are external to that signal line. EMC measures the ability of a circuit to absorb energy from sources other than the logic signals delivered from the next driver down the line. Signal energy from other signals in the system is often coupled via capacitance or inductance into the unprotected lines. EMI measures the opposite effect, the ability of a signal to intrude upon other signals in the system. These functions are complementary and bi-directional; a signal environment that allows transmission of interfering signals will function as a good receiver.

Signals from one point to another

Some of the newer bus interface standards like PCI and the latest Intel memory reference designs have requirements for termination and maximum loading as well as minimum and maximum lengths for the signal lines. The bus specificationsýsignal swing, edge rates, termination, loading, and physical dimensions for minimum separation and maximum lengthýdefine the signal environment. They also prevent a specification-compliant design from developing signal interference and integrity problems.

For non-standard buses, interfaces, and the rest of the circuitry, designers need to work on managing the high-speed signal issues. One option is to examine designs within the proper domain; identify the lines that absolutely must have the high speeds and develop interfaces with small signal swings that operate in a controlled impedance. Maintaining careful control over the signal loading and transmission characteristics greatly improves the likelihood of getting the desired signal with minimal error and distortion.

The most aggressive semiconductor processes use a supply voltage of less than 2 V, which helps to reduce power consumption while also improving signal integrity, but at the expense of reduced noise immunity. Power and signal integrity represent functions of voltage and time in relationships such as I=Cdv/dt or V=Ldi/dt, whereas noise immunity reflects the ratio of noise amplitude to total signal swing. For instance, a 100-mV average noise signal proves insignificant in a 5 V system, but becomes important in a 1.8 V system. The current movement to adopt the latest I/O standardsýsuch as pseudo-emitter coupled logic (PECL), gunning transfer logic (GTL), and other small-signal-swing terminated logic standardsýhelps the power and noise areas without degrading the noise immunity by reducing the energy available for radiation or transmission to other parts of the circuits. Many of the newer I/O standards use a signal swing of a few hundred millivolts into a low-value impedance. The noise doesnýt have the energy to develop more than a few millivolts into the low impedance, so the noise signal becomes less than one percent of the total signal swing.

Instead of struggling to get good signal integrity on all pins, one alternative is to increase the bus bandwidth by maintaining a constant bus transaction frequency while increasing the bus width. The internal bus can be much larger than the external bus, especially within a system on silicon. The designer doesnýt pay as great a penalty in power or area for the wider bus structures as he or she would for interconnections that go to other components. In fact, the wider bus may reduce bus power due to the reduced bus access frequency and much shorter latency for the data, which in turn keeps the processor from having to wait for the data. A bus of 256 to 1024 bits width can deliver many 32-bit words to a processor in one access cycle. The bus can then go quiescent while the processor crunches the data.

This technique of increasing the bus allows very long instruction word (VLIW) processors to pack many instructions into a single word. One of the problems that arises from squeezing more information into a single word is the fact that the system must continually insert blank information into each word to fill the empty spaces. This word-fill operation takes some incremental processing power, which then reduces the overall efficiency of the wider words.

Another alternative to increase data transfer rates combines a number of (slower) signals and converts them to a very high-speed serial stream. The serialization and deserialization requires complex, high-speed circuitry such as an ATM segmentation and reconstruction (SAR) function, but offers attractive options for long runs and point-to-point data transfer. The line characteristics are more easily controlled for a small number of high-speed paths than for a wide bus structure. Some of the very high-speed links can convert parallel data to serial data streams at speeds well in excess of 1.2 Gbs. Similarly, the Rambus interface acts as a quasi-serial memory interface to the slower control signals in parallel and the high-speed data in serial links.

Future alternatives

Does it make sense to make faster parts when alternative logic implementations and processing methods may be more efficient? Some problems will be much better served with different implementation vehicles. For example, a 2-month old baby more efficiently processes the view of another human, distinguishing more details and visual information than a Cray Y-MP can in the same amount of time. The infant recognizes its parents relatively independent of orientation or lighting. The eye and brain have significant embedded preprocessing and information encoding that function even prior to sending parallel data streams to the brainýworking at chemical reaction speeds measured in milliseconds. The brainýs ability to process the incoming information depends upon complex image and pattern recognition algorithms, which depend on many more factors than just the light energy impinging on the cones and rods in the eye. The infant simultaneously performs edge enhancement, feature recognition, motion estimation, and image orientation adjustments across the field of vision in a single pass.

Alternatively, image recognition of an object in arbitrary orientation presents a very difficult processing task for a digital system. The byte-parallel, word-serial nature of most processors usually insures that the processor can process only a small number of bytes at a time. The processor may be able to perform the edge enhancement and minimal feature recognition at the same time as other processing, but it needs to process all of the data across the field of view before doing the image orientation portions. Even more complex, motion estimation requires the comparison of multiple fields. Because the digital processor requires many orders of magnitude, it loses all its speed advantages when involved in multidimensional processing.

In other areas, instead of the single value logic we currently use, some data functions and their implementations may be better served by multilevel logic.

Designing multivalued logic encompasses much more data per symbol than just the two levels per bit that we use today. We are already seeing some movement in this direction in applications like the 56-baud modem.

Although the signals are converted to analog for transmission through the phone lines, the modem uses multibit encoding and multilevel signals for data transmission. The quadrature amplitude modulation (QAM) used to encode the data to a analog stream, converts four statesýor two bitsýinto one of four distinct phases of the underlying carrier signal, thereby vastly increasing the data rate without a corresponding increase in bandwidth.

High-speed designs need special design techniques and analysis tools to achieve quality results. The changes in processes as we move up the Mooreýs law curve will continue to increase the active device speeds. However, IC designs will be increasingly dominated by the interconnect. Already, bottlenecks are appearing in computer subsystems, related to the parallel issues of noise, signal levels, and bandwidth. The demands for increased throughput in the systems are counteracted by the limitations of performance improvements. Future designs will have to depend more on designer creativity than process shrinks to yield faster speeds. However, the faster parts will have to contend with more noise and thornier signal integrity issues to function properly.